Hybrid programmable many-core device with on-chip interconnect

Patent metadata

Field	Value
Publication number	US-10635631-B2
Application number	US-201816186248-A
Country	US
Kind code	B2
Filing date	Nov 9, 2018
Priority date	Mar 14, 2013
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

First claim

What is claimed is:

1. A hybrid data processing device, comprising:
a plurality of hardened processors in a first die and arranged in a plurality of logic columns, wherein at least one hardened processor of the plurality of hardened processors comprises a processor core and a memory, wherein at least one processor core comprises floating-point precision;
a plurality of horizontal and vertical connectors in the first die and coupled to the at least one hardened processor of the plurality of hardened processors in the first die, wherein the at least one hardened processor is configured as a hardware accelerator to accelerate a hardware function;
a plurality of programmable logic elements, wherein the at least one hardened processor of the plurality of hardened processors operates at a respective first clock rate is configurable to receive data from at least one programmable logic element of the plurality of programmable logic elements operating at a second clock rate via the plurality of horizontal and vertical connectors, wherein the plurality of horizontal and vertical connectors is compatible with an Advanced eXtensible Interface (AXI) bus protocol, forms a network-on-chip interconnect, and enables dynamic routing between the at least one hardened processor and the at least one programmable logic element;
a hardened data bus that enables static routing between the at least one hardened processor and the at least one programmable logic element; and
an interface configurable to handle at least one synchronization function to convert the data from the first clock rate to the second clock rate different from the first clock rate.

2. The hybrid data processing device of claim 1 , wherein the memory of the at least one hardened processor comprises an instruction memory and a data memory.

3. The hybrid data processing device of claim 1 , comprising addressable memory coupled to the plurality of horizontal and vertical connectors via an input/output interface.

4. A system, comprising:
a plurality of hardened processors, wherein each hardened processor comprises a processor core, wherein the processor core comprises a number of floating-point units, a data memory, and a program memory and at least one hardened processor operates at a respective first clock rate, wherein the at least one hardened processor is configured as a hardware accelerator to accelerate a hardware function;
programmable logic operating at a second clock rate;
an interface that receives data from the programmable logic at the second clock rate, provides the data to the at least one hardened processor of the plurality of hardened processors at the respective first clock rate, and is configured to handle at least one synchronization function to convert the data from the first clock rate to the second clock rate different from the first clock rate; and
a plurality of horizontal and vertical connectors coupled to the at least one hardened processor of the plurality of hardened processors via the interface, wherein the plurality of horizontal and vertical connectors enables dynamic routing between the interface and the programmable logic, forms a network-on-chip interconnect, and is compatible with an Advanced eXtensible Interface (AXI) bus protocol.

5. An electronic device, comprising:
a plurality of interconnect lines in a first die and operating at a first clock rate;
programmable logic coupled to the interconnect lines in the first die; and
a plurality of hardened processors, comprising a first hardened processor that operates at a second clock, is configured as a hardware accelerator to accelerate a hardware function, comprises floating-point precision, and is coupled to the plurality of interconnect lines via an interface configurable to handle at least one synchronization function between the first hardened processor and the plurality of interconnect lines to convert data from the first clock rate to the second clock rate different from the first clock rate, wherein the plurality of interconnect lines enables dynamic routing between the interface and the programmable logic, forms a network-on-chip interconnect, and is compatible with an Advanced eXtensible Interface (AXI) bus protocol, forms a network-on-chip interconnect.

6. The electronic device of claim 5 , wherein the plurality of interconnect lines comprises horizontal and vertical interconnect lines.

7. The electronic device of claim 5 , wherein the first hardened processor of the plurality of hardened processors comprises a program memory and a processor core, wherein the processor core comprises floating-point precision.

8. The electronic device of claim 5 , wherein the at least one synchronization function comprises an interrupt operation.

9. The electronic device of claim 5 , configurable to perform network processing functions.

10. A method to perform data processing in an electronic device comprising a plurality of hardened processors and programmable logic, wherein a first hardened processor is configured as a hardware accelerator to accelerate a hardware function and comprises floating-point precision, comprising:
sending data from the first hardened processor of the plurality of hardened processors to an interface, wherein the first hardened processor operates at a first clock rate;
performing, in the interface, a synchronizing operation to convert the data from the first clock rate to a second clock rate different from the first clock rate; and
providing the data from the interface to a plurality of interconnects coupled to the programmable logic at the second clock rate, wherein the plurality of interconnects enables dynamic routing between the interface and the plurality of interconnects, forms a network-on-chip interconnect, and is compatible with an Advanced eXtensible Interface (AXI) bus protocol, forms a network-on-chip interconnect.

11. The method of claim 10 , wherein the plurality of interconnects comprises vertical and horizontal interconnects.

12. The method of claim 10 , wherein the programmable logic comprises an accelerator function that receives the data.

13. The method of claim 10 , wherein the data processing comprises network packet processing and wherein the data comprises a network package.

14. The hybrid data processing device of claim 1 , wherein the at least one hardened processor is configured for parallel processing.

15. The system of claim 4 , comprising a hardened data bus that enables static routing between the interface and the programmable logic.

16. The hybrid data processing device of claim 1 , wherein the at least one synchronization function comprises an interrupt operation.

17. The hybrid data processing device of claim 1 , configurable to perform network processing functions.

18. The hybrid data processing device of claim 1 , wherein the at least one hardened processor is configured for parallel processing.

19. The system of claim 4 , wherein the at least one synchronization function comprises an interrupt operation.

20. The system of claim 4 , configurable to perform network processing functions.

21. The system of claim 4 , comprising a hardened data bus that enables static routing between the interface and the programmable logic.

22. The electronic device of claim 5 , wherein the programmable logic comprises an accelerator function that receives the data.

23. The electronic device of claim 5 , comprising a hardened data bus that enables static routing between the interface and the pr

Assignees

• Altera Corp

Inventors

• Hutton Michael D
• Krikelis Anargyros

Classifications

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title

• G06F15/76 Primary

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• Y02D10/13

  Cross-Sectional Technologies · mapped topic

• Y02D10/12

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title