Clustering Computational Workloads for Efficient Allocation of Hardware Resources
US-2025278304-A1 · Sep 4, 2025 · US
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Hutton Michael D patents
Hutton Michael D is listed as an inventor on 29 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hutton Michael D |
| Total patents | 29 |
| First publication | Jan 29, 2015 |
| Latest publication | Sep 4, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Clock synthesis for frequency scaling in programmable logic designs
US-11646739-B2 · May 9, 2023 · US
Hybrid programmable many-core device with on-chip interconnect
US-11256656-B2 · Feb 22, 2022 · US
Clock synthesis for frequency scaling in programmable logic designs
US-2022014204-A1 · Jan 13, 2022 · US
Clock synthesis for frequency scaling in programmable logic designs
US-11177811-B2 · Nov 16, 2021 · US
Hybrid programmable many-core device with on-chip interconnect
US-2020257651-A1 · Aug 13, 2020 · US
Hybrid programmable many-core device with on-chip interconnect
US-10635631-B2 · Apr 28, 2020 · US
Hybrid programmable many-core device with on-chip interconnect
US-2019121783-A1 · Apr 25, 2019 · US
Clock synthesis for frequency scaling in programmable logic designs
US-2019097637-A1 · Mar 28, 2019 · US
Hybrid programmable many-core device with on-chip interconnect
US-10127190-B2 · Nov 13, 2018 · US
Recent patents
Latest publications not already listed above.
Configurable storage circuits with embedded processing and control circuitry
US-9983990-B1 · May 29, 2018 · US
Hybrid programmable many-core device with on-chip interconnect
US-2018089139-A1 · Mar 29, 2018 · US
Hybrid programmable many-core device with on-chip interconnect
US-9830300-B2 · Nov 28, 2017 · US
Field programmable gate array with integrated application specific integrated circuit fabric
US-9705506-B2 · Jul 11, 2017 · US
Configurable register circuitry for error detection and recovery
US-9583218-B1 · Feb 28, 2017 · US
Hybrid programmable many-core device with on-chip interconnect
US-2017024355-A1 · Jan 26, 2017 · US
Hybrid programmable many-core device with on-chip interconnect
US-9471537-B2 · Oct 18, 2016 · US
Mapping network applications to a hybrid programmable many-core device
US-9471388-B2 · Oct 18, 2016 · US
Error resilient packaged components
US-9294092-B2 · Mar 22, 2016 · US
Configurable hybrid adder circuitry
US-9292474-B1 · Mar 22, 2016 · US
Methods and tools for designing integrated circuits with auto-pipelining capabilities
US-9251300-B2 · Feb 2, 2016 · US
Memory blocks with shared address bus circuitry
US-9178513-B1 · Nov 3, 2015 · US
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers
US-9172378-B1 · Oct 27, 2015 · US
Apparatus for field-programmable gate array with configurable architecture and associated methods
US-9165931-B1 · Oct 20, 2015 · US
Methods and apparatus for building bus interconnection networks using programmable interconnection resources
US-9166599-B1 · Oct 20, 2015 · US
Register retiming technique
US-9053274-B1 · Jun 9, 2015 · US
Methods and tools for designing integrated circuits with auto-pipelining capabilities
US-2015121319-A1 · Apr 30, 2015 · US
Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew
US-8997029-B1 · Mar 31, 2015 · US
Error resilient packaged components
US-2015028918-A1 · Jan 29, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Altera Corp | 24 |
| Intel Corp | 4 |
| Hutton Michael D | 2 |
| Schleicher Ii James G | 1 |
| Mansur Daniel R | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| Y02D10/00 | 13 |
| G06F15/7867 | 10 |
| G06F15/76 | 9 |
| G06F30/34 | 8 |
| G06F30/396 | 5 |