Apparatus and method for monitoring and predicting reliability of an integrated circuit

Patent metadata

Field	Value
Publication number	US-10634714-B2
Application number	US-201615051571-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	Feb 23, 2016
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

Described is an apparatus which comprises: a first array of reliability monitors including first and second reliability monitors, wherein the first and second reliability monitors include first and second switches and first and second conductors, wherein the first and second switches are coupled to first and second conductors, respectively; and first and second comparators coupled to the first and second switches, respectively. Described is an apparatus which comprises: a conductor formed on a metal layer; a switch having a source terminal coupled to the conductor, and a drain terminal coupled to a power supply node, wherein the switch is controllable by a controller; and a comparator having a first input coupled to the power supply node and to the switch, wherein the comparator includes a second input coupled to an adjustable reference.

First claim

What is claimed is:

1. An apparatus comprising:
a first array of reliability monitors including first and second reliability monitors, wherein the first and second reliability monitors include first and second switches and first and second conductors, and wherein the first and second switches are coupled to the first and second conductors, respectively; and
first and second comparators coupled to the first and second switches, respectively,
wherein the first reliability monitor includes a multiplexer which is to select one of various locations of the first conductor to electrically couple to the first switch.

2. The apparatus of claim 1 , wherein the first and second switches are coupled to a power supply node.

3. The apparatus of claim 1 comprises a controller to control when to turn on or off the first and second switches.

4. The apparatus of claim 1 , wherein one end of the first conductor is coupled to the first switch while a second end of the first conductor is coupled to ground, and wherein one end of the second conductor is coupled to the second switch while a second end of the second conductor is coupled to ground.

5. The apparatus of claim 1 comprises a reference node coupled to the first and second comparators, wherein the reference node is to provide a reference voltage which is operable to be varied.

6. The apparatus of claim 1 , wherein the first and second conductors are of a same metal layer type such that the first conductor has a different length or width than a length or width of the second conductor.

7. The apparatus of claim 1 , wherein the first and second conductors are of different metal layer types such that the first conductor has a different length or width than a length or width of the second conductor.

8. The apparatus of claim 1 , wherein the first and second conductors are of different metal layer types such that the first conductor has a same length or width as a length or width of the second conductor.

9. The apparatus of claim 1 , wherein each location of the various locations is to indicate a different conducting length of the first conductor.

10. The apparatus of claim 1 comprises:
a second array of reliability monitors including first and second reliability monitors, wherein the first and second reliability monitors of the second array include first and second switches and first and second conductors, and wherein the first and second switches of the second array are coupled to first and second conductors of the second array, respectively; and
a multiplexer which is operable to enable one of the first and second arrays of reliability monitors according to one or more performance conditions indicated by a controller.

11. The apparatus of claim 10 , wherein the one or more performance conditions include at least one of: power supply level and clock frequency.

12. An apparatus comprising:
a conductor on a metal layer;
a switch having a source terminal coupled to the conductor, and a drain terminal coupled to a power supply node, wherein the switch is controllable by a controller; and
a comparator having a first input coupled to the power supply node and to the switch, wherein the comparator includes a second input coupled to an adjustable reference.

13. The apparatus of claim 12 , wherein the controller is to turn on the switch to electrically couple the conductor to the power supply node when one or more circuits in a region of the conductor are active.

14. The apparatus of claim 13 , wherein the controller is to turn off the switch to electrically uncouple the conductor from the power supply node based on the one or more circuits in the region of the conductor being inactive.

15. The apparatus of claim 12 comprises a multiplexer which is to select one of various locations of the conductor to electrically couple the conductor to the switch, wherein each location of the various locations is to indicate a different conducting length of the conductor.

16. The apparatus of claim 12 , wherein an output of the comparator is to be received by a logic which is operable to alert or predict a reliability indicator associated with the conductor.

17. The apparatus of claim 16 , wherein the reliability indicator is electro-migration.

18. A system comprising:
a memory;
a processor coupled to the memory, the processor including:
a processor core which includes:
a first array of electro-migration (EM) monitors including first and second EM monitors, wherein the first and second EM monitors include first and second switches and first and second conductors, wherein the first and second switches are coupled to the first and second conductors, respectively; and
first and second comparators coupled to the first and second switches, respectively; and
an input-output (IO) domain coupled to the processor core and located along a periphery of the processor, wherein the IO domain includes:
a second array of EM monitors including first and second EM monitors, wherein the first and second EM monitors of the second array include first and second switches and first and second conductors, wherein the first and second switches are coupled to the first and second conductors, respectively; and
third and fourth comparators coupled to the third and fourth switches, respectively; and

a wireless interface to allow the processor to communicate with another device.

19. The system of claim 18 , wherein the first EM monitor of the first array includes a multiplexer which is to select one of various locations of the first conductor to electrically couple to the first switch, and wherein each location of the various locations is to indicate a different conducting length of the first conductor.

20. The system of claim 18 , wherein outputs of the first, second, third, and fourth comparators are to be received by a logic which is operable to alert or predict reliability indicators associated with the processing core and the IO domain.

21. The system of claim 18 , wherein:
the first and second conductors are of different metal layer types such that the first conductor has a same length or width as a length or width of the second conductor;
the first and second conductors are of different metal layer types such that the first conductor has a different length or width than a length or width of the second conductor; or
the first and second conductors are of same metal layer type such that the first conductor has a different length or width than a length or width of the second conductor.

22. An apparatus comprising:
a first array of reliability monitors including first and second reliability monitors, wherein the first and second reliability monitors include first and second switches and first and second conductors, and wherein the first and second switches are coupled to the first and second conductors, respectively; and
first and second comparators coupled to the first and second switches, respectively,
wherein the first and second conductors are of a same metal layer hierarchy such that the first conductor has a different length or width than a length or width of the second conductor.

23. The apparatus of claim 22 , wherein the first and second switches are coupled to a power supply node, and wherein the first reliability monitor includes a multiplexer which is to select one of various locations of the first conductor to electrically couple to the first switch.

Assignees

• Intel Corp

Inventors

• Le Huy
• Mayeh Mona
• Zia Victor
• Kwasnick Robert F

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P74/00

  Testing or measuring during manufacture or treatment of wafers, substrates or devices · CPC title

• G01R31/2858 Primary

  Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection · CPC title

• H04Q2213/13162

  Fault indication and localisation · CPC title