Circuit to detect previous use of computer chips using passive test wires

Patent metadata

Field	Value
Publication number	US-9791499-B2
Application number	US-201514602544-A
Country	US
Kind code	B2
Filing date	Jan 22, 2015
Priority date	May 20, 2014
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A test structure and method to detect open circuits due to electromigration or burn-out in test wires and inter-level vias. Electromigration occurs when current flows through circuit wires leading to a circuit interruption within the wire. The test structure is a passive test wire arranged in one of several configurations within the circuit of a computer chip. The dimensions and resistances of test wires can vary according to the test structure configuration. Each test wire is measured for an electrical discontinuity after the computer chip is powered-on. If a wiring interruption is detected, it is concluded that the chip had been powered-on before.

First claim

What is claimed is:

1. A test structure for detecting whether a computer chip has been previously used, the test structure comprising:
an array of passive test wires extending between a voltage source and a ground to form a circuit integrated into the computer chip;
wherein each passive test wire of the array of test wires is of a different length, width, or thickness, such that each of the passive test wires of the array of test wires remains continuous for a different amount of time upon an application of power;
wherein each of the passive test wires are measured for an electrical discontinuity after the computer chip is powered on;
wherein each of the passive test wires are configured to be activated only by applying power to the computer chip for a specified amount of time, such that the electrical discontinuity occurs only if the computer chip was used for the specified amount of time;
the array of passive test wires is coupled to a logic circuit; and
the logic circuit is arranged to determine a length of time the computer chip was previously in use based on the current flowing through each of the passive test wires.

2. The test structure of claim 1 , wherein the passive test wire is connected to an open-circuit measurement circuit, wherein the open-circuit measurement circuit is configured to measure an electrical discontinuity in the passive test wire after a computer chip is powered-on.

3. The test structure of claim 2 , wherein the open-circuit measurement circuit provides information to a digital output about a current flowing through the passive test wire.

4. The test structure of claim 1 , wherein the passive test wire is made of any conducting or semi-conducting material.

5. The test structure of claim 1 , wherein the passive test wire is connected to a current-limiting resistor.

6. The test structure of claim 1 , wherein the passive test wire is connected to a current-limiting field-effect transistor (FET).

7. The test structure of claim 1 , wherein the passive test wire is in proximity to a heating wire.

8. The test structure of claim 1 , wherein the passive test wire is composed of a series of interconnected via structures.

9. The test structure of claim 1 , wherein the passive test wire is connected to a switch.

10. The test structure of claim 3 , wherein the open-circuit measurement circuit is a logic “OR” circuit.

11. The test structure of claim 3 , wherein the digital output further comprises:
a readout configured to display whether the passive test wire contains an electrical discontinuity; or
a scan chain configured to register information on whether the passive test wire contains an electrical discontinuity over a specified time period.

Assignees

• IBM

Inventors

• Jenkins Keith A
• Linder Barry P
• Stawiasz Kevin G

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G06F11/00

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G01R31/2858

  Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection · CPC title

• H01L22/34

  Electricity · mapped topic