Stacked die semiconductor package with electrical interposer

Patent metadata

Field	Value
Publication number	US-10629575-B1
Application number	US-201816219277-A
Country	US
Kind code	B1
Filing date	Dec 13, 2018
Priority date	Dec 13, 2018
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A semiconductor chip assembly includes first and second semiconductor dies that each include opposite facing upper and lower sides and an outer edge side, and an electrical interposer having opposite facing first and second conductive surfaces and a conductive connection between the conductive surfaces. The second semiconductor die is mounted on top of the first semiconductor die and the interposer such that the lower side of the second semiconductor die faces the first semiconductor die and the interposer, a first lateral section of the second semiconductor die at least partially covers the upper side of the first semiconductor die, and a second lateral section of the second semiconductor die extends past the outer edge side of the first semiconductor die. The first conductive surface is electrically connected to a first terminal that is disposed on a lower side of the second semiconductor die.

First claim

What is claimed is:

1. A semiconductor chip assembly, comprising:
first and second semiconductor dies, the first and second semiconductor dies each comprising opposite facing upper and lower sides and an outer edge side extending between the respective upper and lower sides of the first and second semiconductor dies; and
an electrical interposer comprising a first conductive surface disposed at a first end, a second conductive surface disposed at a second end that is opposite from the first end, and a conductive connection between the first and second conductive surfaces;
wherein the second semiconductor die is mounted on top of the first semiconductor die and the interposer such that:
the lower side of the second semiconductor die faces the upper side of the first semiconductor die and the first end of the interposer;
a first lateral section of the second semiconductor die at least partially covers the upper side of the first semiconductor die; and
a second lateral section of the second semiconductor die extends past the outer edge side of the first semiconductor die and over the first end of the interposer,

wherein the first conductive surface is electrically connected to a first terminal of the second semiconductor die that is disposed on the lower side of the second semiconductor die.

2. The semiconductor chip assembly of claim 1 , wherein the first semiconductor die comprises a third terminal having a conductive surface that is disposed at or above the upper side of the first semiconductor die, and wherein the first conductive surface of the interposer is substantially coplanar with the conductive surface of the third terminal.

3. The semiconductor chip assembly of claim 2 , wherein the conductive surface of the third terminal is disposed above the upper side of the first semiconductor die, and wherein the first conductive surface protrudes away from an insulating surface of the first end of the electrical interposer.

4. The semiconductor chip assembly of claim 2 , wherein the electrical interposer forms an enclosed loop around a central opening, and wherein the first semiconductor die is disposed within the central opening.

5. The semiconductor chip assembly of claim 4 , wherein the second semiconductor die completely covers the first semiconductor die and laterally extends past the outer edge side of the first semiconductor in all directions, and wherein the enclosed loop is at least partially underneath the second semiconductor die.

6. The semiconductor chip assembly of claim 5 , wherein the interposer comprises an insulative body comprising electrically insulating sidewalls that extend between the first and second ends of the interposer, and wherein the conductive connection is provided by an electrical conductor that is contained within the insulative body.

7. The semiconductor chip assembly of claim 6 , wherein the interposer is formed from a printed circuit board substrate, and wherein the conductive connection comprises a conductive via that extends through one or more layers of the printed circuit board substrate.

8. The semiconductor chip assembly of claim 6 , wherein the interposer is formed from a molded interconnect substrate comprising one or more molded plastic layers and one or more metallization layers arranged on the one or more molded plastic layers, and wherein the conductive connection comprises a conductive trace formed in the one or more metallization layers.

9. The semiconductor chip assembly of claim 4 , wherein the interposer comprises:
a planar sheet of conductive sheet metal;
one or more protrusions extending from edge sides of the central opening;
vertical posts located at ends of the one or more protrusions; and
recessed surfaces in the one or more protrusions between edge sides of the central opening and the vertical posts.

10. The semiconductor chip assembly of claim 9 , wherein the recessed surfaces face away from the lower side of the second semiconductor die and the first conductive surface is provided by a flat surface of the one or more protrusions that is opposite from one of the recessed surfaces.

11. The semiconductor chip assembly of claim 9 , wherein the recessed surfaces face towards the lower side of the second semiconductor die and the first conductive surface is provided by a surface of the vertical post that is immediately adjacent to one of the recessed surfaces.

12. A semiconductor chip assembly, comprising:
an amplifier die comprising opposite facing upper and lower sides, and an input terminal disposed on the upper side of the amplifier die,
a controller die comprising opposite facing upper and lower sides, an input terminal and an output terminal disposed on the lower side of the controller die;
an electrical interposer comprising a first conductive surface disposed at a first end, a second conductive surface disposed at a second end that is opposite from the first end, and a conductive connection between the first and second conductive surfaces; and
a planar connection interface disposed at or below the lower side of the first semiconductor die, the planar connection interface comprising a plurality of conductive I/O terminals,
wherein the controller die is mounted on top of the amplifier die such that a first lateral portion of the controller die comprising the output terminal of the controller die is aligned with and electrically connected to the input terminal of the amplifier die, and a second lateral portion of the controller die comprising the input terminal of the controller die is aligned with and electrically connected to the first conductive surface of the interposer, and
wherein the electrical interposer provides an electrical connection between a first one of the I/O terminals and the input terminal of the controller die.

13. The semiconductor chip assembly of claim 12 , wherein the semiconductor chip assembly further comprises an electrically insulating mold compound body that encapsulates the controller die and the interposer, wherein the lower side of the first semiconductor die and the second conductive surface are exposed at a bottom side of the mold compound body, and wherein the first I/O terminal is provided by the second conductive surface.

14. A method of providing a semiconductor chip assembly, the method comprising:
providing first and second semiconductor dies, the first and second semiconductor dies each comprising opposite facing upper and lower sides and an outer edge side extending between the respective upper and lower sides of the first and second semiconductor dies;
providing an electrical interposer comprising a first conductive surface disposed at a first end, a second conductive surface disposed at a second end that is opposite from the first end, and a conductive connection between the first and second conductive surfaces; and
mounting the second semiconductor die on top of the first semiconductor die and the interposer such that:
the lower side of the second semiconductor die faces the upper side of the first semiconductor die and the first end of the interposer;
a first lateral section of the second semiconductor die at least partially covers the upper side of the first semiconductor die; and
a second lateral section of the second semiconductor die extends past the outer edge side of the first semiconductor die and over the first end of the interposer, and

electrically connecting the first conductive surface to a first conductive terminal that is disposed on the lower side of the second semiconductor die.

15. The method of claim 14 , wherein the first semiconductor die comprises a third terminal havin

Assignees

• Infineon Technologies Ag
• Infineon Techologies Ag

Inventors

• Scharf Thorsten
• Ahrens Carsten
• Brech Helmut
• Gruber Martin
• Meyer Thorsten
• Zigldrum Matthias

Classifications

• H01L25/16 Primary

  Electricity · mapped topic

• H01L21/561

  Electricity · mapped topic

• H01L24/97

  Electricity · mapped topic

• H01L2924/1433

  Electricity · mapped topic

• H01L21/565

  Electricity · mapped topic