Semiconductor device

Patent metadata

Field	Value
Publication number	US-10629546-B2
Application number	US-201816113204-A
Country	US
Kind code	B2
Filing date	Aug 27, 2018
Priority date	Jan 29, 2018
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A semiconductor device including a substrate including a central region and a peripheral region surrounding the central region, a semiconductor integrated circuit in the central region, and a three-dimensional crack detection structure in the peripheral region, the three-dimensional crack detection structure surrounding the central region, the three-dimensional crack detection structure including a first pattern, a second pattern, and a third pattern, the first and second patterns extending in a first direction and spaced apart from each other, the third pattern being parallel to an upper surface of the substrate and connecting the first and second patterns to each other, the third pattern including a first portion and a second portion, the first and second portions extending in a second direction and a third direction respectively, the second direction intersecting with the first direction, the third direction intersecting with the first and second directions may be provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a central region and a peripheral region surrounding the central region;
a semiconductor integrated circuit in the central region; and
a three-dimensional crack detection structure in the peripheral region, the three-dimensional crack detection structure surrounding the central region, the three-dimensional crack detection structure including a first pattern, a second pattern, and a third pattern, the first and second patterns extending in a first direction and spaced apart from each other, the third pattern being parallel to an upper surface of the substrate and connecting the first and second patterns to each other, the third pattern including a first portion and a second portion, the first and second portions extending in a second direction and a third direction respectively, the second direction intersecting with the first direction, the third direction intersecting with the first and second directions.

2. The semiconductor device of claim 1 , wherein the first portion of the third pattern is between the second portion of the third pattern and the first pattern.

3. The semiconductor device of claim 1 , further comprising:
a crack prevention structure in the peripheral region,
wherein the three-dimensional crack detection structure is between the crack prevention structure and the semiconductor integrated circuit.

4. The semiconductor device of claim 3 , wherein the crack prevention structure is configured to prevent a crack generated by an external factor from entering the semiconductor integrated circuit.

5. The semiconductor device of claim 1 , wherein the three-dimensional crack detection structure further comprises a fourth pattern on the first, second, and third patterns and parallel to the upper surface of the substrate, one end of the fourth pattern is connected to an input terminal, and the other end of the fourth pattern is connected to an output terminal.

6. The semiconductor device of claim 1 , wherein the three-dimensional crack detection structure further comprises a fourth pattern extending in the first direction and spaced apart from the first and second patterns, and a fifth pattern connecting the second and fourth patterns to each other.

7. The semiconductor device of claim 6 , wherein the three-dimensional crack detection structure further comprises a sixth pattern extending in the first direction and spaced apart from the first pattern, the second pattern, and the fourth pattern, and a seventh pattern connecting the fourth and sixth patterns to each other.

8. The semiconductor device of claim 7 , wherein the third pattern and the seventh pattern include poly-crystal material, and the fifth pattern includes metal.

9. The semiconductor device of claim 1 , wherein at least a part of the third pattern is configured to be destroyed by a nano crack penetrating into the third pattern.

10. A semiconductor device comprising:
a substrate including a first region and a second region surrounding the first region;
a first semiconductor structure in the first region; and
a second semiconductor structure in the second region, the second semiconductor structure including a crack detection structure (CDS), the CDS including a net type pattern both ends of which are connected to a first input terminal and a first output terminal, respectively, the net type pattern including a plurality of vertical patterns parallel to each other, a plurality of upper patterns connecting upper portions of the plurality of vertical patterns, and a plurality of lower patterns connecting lower portions of the plurality of vertical patterns, a length of each of the plurality of upper patterns being smaller than a length of each of the plurality of lower patterns.

11. The semiconductor device of claim 10 , further comprising:
a crack prevention structure in the second region,
wherein the CDS is between the crack prevention structure and the first semiconductor structure.

12. The semiconductor device of claim 11 , wherein the crack prevention structure is configured to prevent a crack generated by an external factor from entering the first semiconductor structure.

13. The semiconductor device of claim 10 , wherein the CDS further comprises a ring type pattern on the net type pattern, and first and second terminals of the ring type pattern are connected to a second input terminal and a second output terminal, respectively.

14. The semiconductor device of claim 10 , wherein a length of each of the plurality of upper patterns is smaller than a length of each of the plurality of lower patterns.

15. The semiconductor device of claim 10 , wherein at least a part of the plurality of lower patterns is configured to be destroyed by a nano crack penetrating into the at least a part of plurality of lower patterns.

16. The semiconductor device of claim 10 , wherein the plurality of upper patterns includes metal.

17. The semiconductor device of claim 10 , wherein the plurality of lower patterns includes poly-crystal material.

18. A semiconductor device comprising:
a substrate including a central region and a peripheral region surrounding the central region;
a semiconductor integrated circuit in the central region; and
a three-dimensional crack detection structure in the peripheral region and surrounding the central region, the three-dimensional crack detection structure including a first vertical pattern and a second vertical pattern, the first and second vertical patterns spaced apart from each other and extending in a first direction, the first and second vertical patterns being along a first line surrounding the central region, a horizontal pattern connecting the first and second vertical patterns to each other, the horizontal pattern being parallel to an upper surface of the substrate, at least a part of the horizontal pattern being outside the first line.

19. The semiconductor device of claim 18 , wherein at least a part of the first horizontal pattern is formed in a snake shape.

20. The semiconductor device of claim 18 , wherein the first horizontal pattern includes poly-crystal material.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Roh Jung Hyun

Classifications

• H10W90/00

  Package configurations · CPC title

• G01R31/2607

  Circuits therefor (G01R31/2642 takes precedence) · CPC title

• G01R31/2831

  Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00) · CPC title

• H01L23/562 Primary

  Electricity · mapped topic

• H01L22/34

  Electricity · mapped topic