Stack type semiconductor device and method of fabricating and testing the same

Patent metadata

Field	Value
Publication number	US-9293381-B2
Application number	US-201414495213-A
Country	US
Kind code	B2
Filing date	Sep 24, 2014
Priority date	Apr 18, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

There are proposed a stack type semiconductor device and a method of fabricating and testing the same. A stack type semiconductor device according to an embodiment of the present invention includes a plurality of contact pads externally exposed, a via array electrically connected to the contact pads, a semiconductor substrate configured to have vias, forming the via array, electrically conductive with each other or insulated from each other, and a bias pad configured to supply a bias to the semiconductor substrate, wherein the semiconductor substrate may be subject to back-grinding.

First claim

What is claimed is:

1. A method of fabricating each of dies of a stack type semiconductor device, the method comprising:
forming a first type well having a first height on a lower side of a semiconductor substrate;
forming one or more second type doping regions within the first type well at bottoms of regions where vias are expected to be formed;
forming a first type doping region within the first type well at a bottom of a region where a bias contact is expected to be formed;
forming the vias to be electrically connected to the second type doping regions, respectively;
forming the bias contact to be electrically connected to the first type doping region;
forming contact pads electrically connected the respective vias; and
forming a bias pad electrically connected to the bias contact.

2. The method according to claim 1 , further comprising performing a test by supplying a positive voltage or a negative voltage to the bias pad.

3. The method according to claim 2 , further comprising performing back-grinding on the semiconductor substrate up to a position equal to or higher than the first height, after performing the test.

4. The method according to claim 1 , further comprising forming a wire layer configured to electrically couple the vias and the respective contact pads before forming the contact pads, after forming the vias.

5. The method according to claim 4 , further comprising performing a test by supplying a positive voltage or a negative voltage to the bias pad.

6. The method according to claim 5 , further comprising performing back-grinding on the semiconductor substrate up to a position equal to or higher than the first height, after performing the test.

Assignees

• Sk Hynix Inc

Inventors

• Yoo Sun Jong

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W90/00

  Package configurations · CPC title