IC unit and methond of manufacturing the same, and electronic device including the same

Patent metadata

Field	Value
Publication number	US-10629498-B2
Application number	US-201715722423-A
Country	US
Kind code	B2
Filing date	Oct 2, 2017
Priority date	Sep 30, 2016
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

First claim

We claim:

1. An Integrated Circuit (IC) unit, comprising:
a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate, wherein in the first device, the channel layer comprises a first portion and a second portion separated from each other, the first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer;
a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device; and
a second gate stack surrounding a periphery of the channel layer of the second device,
wherein the channel layer of the second device is substantially coplanar with the second gate stack.

2. The IC unit according to claim 1 , wherein
the first device is a p-type device, and the second device is an n-type device; or
the first device is an n-type device, and the second device is a p-type device.

3. The IC unit according to claim 1 , wherein the channel layer of the second device is substantially aligned to one of the first portion and the second portion of the channel layer of the first device in a vertical direction.

4. The IC unit according to claim 3 , wherein
the second source/drain layer of the first device and the first source/drain layer of the second device protrude, with respect to the second source/drain layer of the second device, towards the other one of the first portion and the second portion of the channel layer of the first device, and
the first gate stack and the second gate stack protrude, with respect to the second source/drain layer of the second device, in a direction opposite to that in which the second source/drain layer of the first device and the first source/drain layer of the second device protrude.

5. The IC unit according to claim 1 , wherein the first source/drain layer of the second device extends on substantially an entire top surface of the second source/drain layer of the first device.

6. The IC unit according to claim 1 , wherein the first source/drain layer of the second device has its periphery substantially coinciding with that of the second source/drain layer of the first device.

7. The IC unit according to claim 6 , wherein
each of the first source/drain layer of the second device and the second source/drain layer of the first device a first main-body portion positioned above the first portion of the channel layer of the first device, a second main-body portion positioned above the second portion of the channel layer of the first device, and a connection portion between the first main-body portion and the second main-body portion, and
wherein the first main-body portion of each of the first source/drain layer of the second device and the second source/drain layer of the first device has it periphery extending substantially parallel to that of the first portion of the channel layer of the first device, and the second main-body portion of each of the first source/drain layer of the second device and the second source/drain layer of the first device has it periphery extending substantially parallel to that of the second portion of the channel layer of the first device.

8. The IC unit according to claim 1 , wherein the first device and the second device are of different conductivity types, and the IC unit further comprises:
a first contact in electrical contact with the second source/drain layer of the second device;
a second contact in electrical contact with the second source/drain layer of the first device and the first source/drain layer of the second device;
a third contact in electrical contact with the first source/drain layer of the first device; and
a fourth contact in electrical contact with the first gate stack and the second gate stack.

9. The IC unit according to claim 8 , wherein
the first contact is positioned above and extends onto the second source/drain layer of the second device;
the second contact is positioned above and extends onto the first source/drain layer of the second device;
the third contact is positioned above and extends onto the first source/drain layer of the first device; and
the fourth contact is positioned above and extends onto the first gate stack and the second gate stack.

10. The IC unit according to claim 8 , wherein the IC unit constitutes an inverter,
wherein in a case where the first device is a p-type device, and the second device is an n-type device, the first contact is connectable to ground, the third contact is connectable to a supply voltage, the fourth contact is operable to receive an input signal, and the second contact is operable to output an inverted signal which is an inverted version of the input signal, or
wherein in a case where the first device is an n-type device, and the second device is a p-type device, the first contact is connectable to a supply voltage, the third contact is connectable to ground, the fourth contact is operable to receive an input signal, and the second contact is operable to output an inverted signal which is an inverted version of the input signal.

11. The IC unit according to claim 1 , wherein the channel layer of the first device and the channel layer of the second device each comprise a single-crystalline semiconductor material.

12. The IC unit according to claim 11 , wherein the first and second source/drain layers of the first device and the first and second source/drain layers of the second device each comprise a single-crystalline semiconductor material.

13. The IC unit according to claim 12 , wherein the single-crystalline semiconductor material for the channel layer and the single-crystalline semiconductor material for the source/drain layer have the same crystal structure.

14. The IC unit according to claim 1 , wherein
in the second device, the channel layer has its periphery recessed inwards with respect to that of the first source/drain layer and to that of the second source/drain layer, and the second gate stack is embedded into and self-aligned to the recess, and
in the first device, the channel has its periphery recessed inwards with respect to that of the first source/drain layer and to that of the second source/drain layer, and the first gate stack is embedded into and self-aligned to the recess.

15. The IC unit according to claim 1 , wherein
the channel layer of the second device comprise a semiconductor material different from that of the first and second source/drain layers of the second device, and
the channel layer of the first device comprise a semiconductor material different from that of the first and second source/drain layers of the first device.

16. The IC unit according to claim 1 , wherein the first source/drain layer, the channel layer and the second source/drain layer of the first device and the first source/drain layer, the channel layer and the second source/drain layer of the second device are epitaxial layers on the substrate.

17. The IC unit according to claim 1 , wherein there is a crystalline interface between at least a pair of adjacent ones among the respective source/drain layers and channel layers.

18. An electronic device comprising an Integrated Circuit (IC) having the IC unit according to claim 1 .

19. The electronic device according to claim 18 , further comprising a display operatively coupled to the IC unit and a wireless transce

Assignees

• Inst Of Microelectronics Cas

Inventors

• Zhu Huilong
• Zhu Zhengyong

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/66431

  Electricity · mapped topic

• H01L21/2258

  Electricity · mapped topic

• H01L21/2252

  Electricity · mapped topic

• H01L21/02532

  Electricity · mapped topic