Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9502519-B2
Application number	US-201514636125-A
Country	US
Kind code	B2
Filing date	Mar 2, 2015
Priority date	Jan 19, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a second dielectric layer thereon; forming a drain layer in the first dielectric layer and the second dielectric layer; forming a gate layer on the second dielectric layer; forming a channel layer in the gate layer; forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer; and forming a source layer in the third dielectric layer and the fourth dielectric layer.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
providing a substrate having a first dielectric layer and a second dielectric layer thereon;
forming a drain layer in the first dielectric layer and the second dielectric layer;
forming a gate layer on the second dielectric layer;
forming a first barrier layer between the gate layer and the second dielectric layer;
forming a channel layer in the gate layer;
forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer;
forming a second barrier layer between the gate layer and the third dielectric layer; and
forming a source layer in the third dielectric layer and the fourth dielectric layer.

2. The method of claim 1 , further comprising:
performing a photo-etching process to remove part of the second dielectric layer and part of the first dielectric layer for forming an opening; and
forming the drain layer in the opening.

3. The method of claim 1 , further comprising:
performing a photo-etching process to remove part of the fourth dielectric layer and part of the third dielectric layer for forming an opening; and
forming the source layer in the opening.

4. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer comprise different material, and the third dielectric layer and the fourth dielectric layer comprise different material.

5. The method of claim 1 , wherein the drain layer, the channel layer, and the source layer comprise different material.

6. The method of claim 1 , further comprising:
forming a first barrier layer on the second dielectric layer and the drain layer;
forming the gate layer on the first barrier layer;
forming a second barrier layer on the gate layer;
forming a hard mask on the second barrier layer; and
performing a photo-etching process to remove part of the hard mask, part of the second barrier layer, part of the gate layer, and part of the first barrier layer for forming an opening.

7. The method of claim 6 , further comprising:
forming a work function layer on the hard mask and in the opening;
removing part of the work function layer in the opening to expose the drain layer;
forming a gate dielectric layer on the work function layer and in the opening;
removing part of the gate dielectric layer to expose the drain layer;
forming the channel layer in the opening; and
removing part of the channel layer, part of the gate dielectric layer, part of the work function layer, and the hard mask.

8. A method for fabricating semiconductor device, comprising:
providing a substrate having a first dielectric layer thereon;
forming a drain layer in the first dielectric layer;
forming a second dielectric layer on the first dielectric layer and the drain layer;
forming a gate layer on the second dielectric layer;
forming a first barrier layer between the gate layer and the second dielectric layer;
forming a channel layer in the gate layer and the second dielectric layer;
forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer;
forming a second barrier layer between the gate layer and the third dielectric layer; and
forming a source layer in the third dielectric layer and the fourth dielectric layer.

9. The method of claim 8 , further comprising:
forming a first hard mask on the first dielectric layer;
performing a photo-etching process to remove part of the first hard mask and part of the first dielectric layer for forming an opening;
forming the drain layer in the opening; and
removing part of the drain layer and the first hard mask.

10. The method of claim 8 , further comprising:
performing a photo-etching process to remove part of the fourth dielectric layer and part of the third dielectric layer for forming an opening;
performing an etching process to extend the opening; and
forming the source layer in the opening.

11. The method of claim 8 , wherein the first dielectric layer and the second dielectric layer comprise different material, and the third dielectric layer and the fourth dielectric layer comprise different material.

12. The method of claim 8 , wherein the drain layer, the channel layer, and the source layer comprise different material.

13. The method of claim 8 , further comprising:
forming a first barrier layer on the second dielectric layer and the drain layer;
forming the gate layer on the first barrier layer;
forming a second barrier layer on the gate layer;
forming a second hard mask on the second barrier layer; and
performing a photo-etching process to remove part of the second hard mask, part of the second barrier layer, part of the gate layer, and part of the first barrier layer for forming an opening.

14. The method of claim 13 , further comprising:
forming a work function layer on the second hard mask and in the opening;
removing part of the work function layer in the opening to expose the second dielectric layer;
forming a gate dielectric layer on the work function layer and in the opening;
removing part of the gate dielectric layer to expose the second dielectric layer;
removing part of the second dielectric layer to expose the drain layer;
forming the channel layer in the opening; and
removing part of the channel layer, part of the gate dielectric layer, part of the work function layer and the second hard mask.

15. A semiconductor device, comprising:
a substrate having a first dielectric layer and a second dielectric layer thereon;
a drain layer in the first dielectric layer;
a gate layer on the second dielectric layer;
a first barrier layer between the gate layer and the second dielectric layer;
a channel layer in the gate layer and on the drain layer;
a third dielectric layer and a fourth dielectric layer on the gate layer;
a second barrier layer between the gate layer and the third dielectric layer; and
a source layer in the fourth dielectric layer and on the channel layer, wherein the source layer, the channel layer, and the drain layer comprise different material.

16. The semiconductor device of claim 15 , further comprising:
a gate dielectric layer surrounding the channel layer; and
a work function layer surrounding the gate dielectric layer.

17. The semiconductor device of claim 15 , wherein the widths of the source layer and the drain layer are larger than the width of the channel layer.

18. The semiconductor device of claim 15 , wherein the top surface of the channel layer is even with the top surface of the gate layer.

19. The semiconductor device of claim 18 , wherein the bottom surface of the channel layer is even with the top surface of the first dielectric layer.

Assignees

• United Microelectronics Corp

Inventors

• Chen Hsin-Yu
• Lin Sheng-Hao
• Chiang Huai-Tzu
• Lee Hao-Ming

Classifications

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H01L29/66712

  Electricity · mapped topic