Flipped vertical field-effect-transistor

Patent metadata

Field	Value
Publication number	US-9799655-B1
Application number	US-201615137036-A
Country	US
Kind code	B1
Filing date	Apr 25, 2016
Priority date	Apr 25, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

First claim

What is claimed is:

1. A method for fabricating vertical transistors, the method comprising:
forming a structure comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the first doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area;
flipping the structure;
after flipping the structure, bonding the structure to a second substrate;
removing the first substrate and the insulator layer, the removing exposing the first doped layer;
forming a second contact area in contact with the first doped layer; and
forming at least a second interconnect in contact with the second contact area.

2. The method of claim 1 , wherein the method further comprises:
prior to forming the dielectric layer and the gate layer, forming a first spacer on the fin structure, the dielectric layer and the gate layer being formed on and in contact with the first spacer layer.

3. The method of claim 2 , wherein the method further comprises:
after forming the dielectric layer and the gate layer, forming a second spacer on the fin structure and in contact with the dielectric layer and the gate layer the gate layer.

4. The method of claim 1 , further comprising a third interconnect in contact with the gate layer.

5. The method of claim 1 , further comprising:
forming a dielectric layer in contact with the first interconnect and the first contact area.

6. The method of claim 1 , further comprising:
forming a dielectric layer in contact with the second interconnect and the second contact area.

7. The method of claim 1 , wherein the first and second doped layers are source/drain layers.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Miao Xin
• Xu Wenyu
• Zhang Chen

Classifications

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title