Wafer chuck and processing arrangement

Patent metadata

Field	Value
Publication number	US-10629416-B2
Application number	US-201715412131-A
Country	US
Kind code	B2
Filing date	Jan 23, 2017
Priority date	Jan 23, 2017
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

According to various embodiments, a wafer chuck may include at least one support region configured to support a wafer in a receiving area; a central cavity surrounded by the at least one support region configured to support the wafer only along an outer perimeter; and a boundary structure surrounding the receiving area configured to retain the wafer in the receiving area.

First claim

What is claimed is:

1. A wafer chuck, comprising:
a baseplate comprising electrically conductive material to apply a voltage at the baseplate in order to generate an electrical field;
at least one support region configured to support a wafer in a receiving area;
a central cavity in the baseplate surrounded by the at least one support region configured to support the wafer only along an outer perimeter of the wafer; and
a boundary structure surrounding the receiving area configured to retain the wafer in the receiving area.

2. The wafer chuck of claim 1 ,
wherein the at least one support region comprises a support surface configured to physically contact an edge surface region of an edge region of the wafer, the edge surface region facing the wafer chuck.

3. The wafer chuck of claim 2 ,
wherein the central cavity comprises a bottom surface disposed at a first level less than a second level of the support surface.

4. The wafer chuck of claim 3 ,
wherein the bottom surface is curved.

5. The wafer chuck of claim 1 ,
wherein the boundary structure defines a maximal diameter of the wafer to be received in the receiving area and wherein the at least one support region defines a minimal diameter of the wafer to be received in the receiving area.

6. The wafer chuck of claim 1 ,
wherein the boundary structure, the central cavity, and the at least one support region are concentrically arranged.

7. The wafer chuck of claim 1 ,
wherein the central cavity is provided by a single recessed region.

8. The wafer chuck of claim 1 , further comprising:
a plurality of notches extending from an outer circumference of the wafer chuck into the wafer chuck.

9. The wafer chuck of claim 8 ,
wherein each of the plurality of notches is configured to host a handling pin of a wafer handler to lower the wafer into the receiving area and to raise the wafer out of the receiving area.

10. The wafer chuck of claim 1 , further comprising:
a mounting flange at a side opposite the receiving area to mount the wafer chuck in a processing tool.

11. A processing arrangement comprising:
a processing tool for processing a wafer in a processing region;
a wafer chuck to position the wafer in the processing tool, the wafer chuck comprising:
a baseplate comprising electrically conductive material to apply a voltage at the baseplate in order to generate an electrical field;
at least one support region configured to support the wafer in a receiving area;
a central cavity in the baseplate surrounded by the at least one support region configured to support the wafer only along an outer perimeter of the wafer; and
a boundary structure surrounding the receiving area configured to retain the wafer in the receiving area.

12. The processing arrangement of claim 11 ,
wherein the processing tool is a plasma-processing tool.

13. The processing arrangement of claim 11 ,
wherein the wafer chuck is configured as an electrode.

14. The processing arrangement of claim 11 , further comprising:
a wafer handler to lower the wafer into the receiving area and to raise the wafer out of the receiving area.

15. The processing arrangement of claim 14 ,
wherein the wafer chuck comprises a plurality of notches extending from an outer perimeter of the wafer chuck into the wafer chuck: and
wherein the wafer handler comprises a plurality of handling pins configured to be raised and lowered through the plurality of notches to raise and lower the wafer.

16. The processing arrangement of claim 11 ,
wherein the central cavity comprises a bottom surface disposed at a first level less than a second level of a support surface of the at least one support region.

17. The processing arrangement of claim 11 ,
wherein the central cavity is provided by a single recessed region.

18. The processing arrangement of claim 16 ,
wherein the bottom surface is curved.

19. The processing arrangement of claim 16 , further comprising:
a wafer in the receiving area, wherein the bottom surface of the cavity is equidistantly arranged relative to a surface of the wafer facing the wafer chuck or facing away from the wafer chuck.

Assignees

• Infineon Technologies Ag

Inventors

• Kogler Rudolf
• Steinbrenner Juergen
• Dastel Wolfgang
• Huetter Harald
• Kahn Markus

Classifications

• H10P72/7624

  characterised by the mechanical construction of the susceptor, stage or support · CPC title

• H10P72/7612

  characterised by lifting arrangements, e.g. lift pins · CPC title

• H10P72/7611

  characterised by edge profile or support profile · CPC title

• H10P72/0421

  for drying etching · CPC title

• H10P72/0408

  for drying · CPC title