Reading method for preventing read disturbance and memory using the same

Patent metadata

Field	Value
Publication number	US-9761319-B1
Application number	US-201615344614-A
Country	US
Kind code	B1
Filing date	Nov 7, 2016
Priority date	Nov 7, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A reading method for preventing a read disturbance and a memory using the same are provided. The reading method includes the following steps: At least one of a plurality of string select lines is selected and a predetermined string select voltage is applied to the selected string select line. Only one of a plurality of ground select lines is selected and a predetermined ground select voltage is applied to the selected ground select line.

First claim

What is claimed is:

1. A reading method of a memory, for preventing a read disturbance, the memory including a plurality of strings, the reading method comprising:
selecting at least one of a plurality of string select lines and applying a predetermined string select voltage to the selected string select line;
selecting only one of a plurality of ground select lines and applying a predetermined ground select voltage to the selected ground select line;
selecting at least one of the strings, wherein the selected string is connected to the selected string select line and the selected ground select line, the unselected strings are floating, and a channel potential of each of the unselected strings is boosted to be a predetermined voltage level; and
selecting one of a plurality of word lines, wherein the selected word line is applied a read voltage, and the unselected word line is applied a pass voltage.

2. The reading method of the memory according to claim 1 , wherein the ground select lines are not connected together.

3. The reading method of the memory according to claim 1 , wherein the ground select lines are decoded separately.

4. The reading method of the memory according to claim 1 , wherein the unselected ground select lines are applied 0 voltage.

5. The reading method of the memory according to claim 1 , further comprising:
selecting a plurality of even bit lines or a plurality of odd bit lines to be applied a predetermined bit line voltage.

6. The reading method of the memory according to claim 1 , wherein in the step of selecting the at least one of the string select lines, two of the string select lines are selected.

7. The reading method of the memory according to claim 6 , wherein one of the strings which is connected to one of the selected string select lines and one of a plurality of even bit lines and another one of the strings which is connected to another one of the selected string select lines and one of a plurality of odd bit lines are regarded as one page.

8. A memory, comprising:
a plurality of string select lines, wherein when the memory is read, at least one of the string select lines is selected by a decoder, and a predetermined string select voltage is applied to the selected string select line; and
a plurality of ground select lines, wherein when the memory is read, only one of the ground select lines is selected by the decoder, and a predetermined ground select voltage is applied to the selected ground select line;
wherein when the memory is read, at least one of the string select lines and only one of the ground select lines is selected by the decoder are selected by the decoder at the same time.

9. The memory according to claim 8 , wherein the ground select lines are not connected together.

10. The memory according to claim 8 , wherein the ground select lines are decoded separately by the decoder.

11. The memory according to claim 8 , wherein the unselected ground select lines are applied 0 voltage.

12. The memory according to claim 8 , further comprising:
a plurality of strings, wherein at least one of the strings is selected, and the selected string is connected to the selected string select line and the selected ground select line.

13. The memory according to claim 12 , wherein the unselected strings are floating.

14. The memory according to claim 13 , wherein a channel potential of each of the unselected strings is boosted to be a predetermined voltage level.

15. The memory according to claim 8 , further comprising:
a plurality of even bit lines and a plurality of odd bit lines, wherein the even bit lines or the odd bit lines are selected to be applied a predetermined bit line voltage.

16. The memory according to claim 8 , wherein two of the string select lines are selected.

17. The memory according to claim 16 , further comprising:
a plurality of strings, wherein one of the strings which is connected to one of the selected string select lines and one of a plurality of even bit lines and another one of the strings which is connected to another one of the selected string select lines and one of a plurality of odd bit lines are regarded as one page.

Assignees

• Macronix Int Co Ltd

Inventors

• Chang Kuo-Pin
• Yeh Teng-Hao
• Lue Hang-Ting

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title