Executing load-store operations without address translation hardware per load-store unit port

Patent metadata

Field	Value
Publication number	US-10628158-B2
Application number	US-201715825625-A
Country	US
Kind code	B2
Filing date	Nov 29, 2017
Priority date	Oct 6, 2017
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.

First claim

What is claimed is:

1. A computer-implemented method for out-of-order execution of one or more instructions by a processing unit, the method comprising:
receiving, by a load-store unit (LSU) of the processing unit, an out-of-order (OoO) window of instructions comprising a plurality of instructions to be executed OoO; and
issuing, by the LSU, instructions from the OoO window, the issuing comprising:
selecting an instruction from the OoO window, the instruction using an effective address;
in response to the instruction being a load instruction:
determining whether the effective address is present in an effective address directory (EAD); and
in response to the effective address being present in the EAD, issuing the load instruction using the effective address; and
in response to the effective address of the load instruction not being present in the EAD, determining a real address of the load instruction mapped to the effective address from an effective-real translation (ERT), and issuing the load instruction using the real address of the load instruction.

2. The computer-implemented method of claim 1 , wherein issuing the load instruction comprises creating an entry for the load instruction in a load reorder queue, wherein the entries in the load reorder queue are executed out of order.

3. The computer-implemented method of claim 1 , wherein issuing the store instruction comprises creating an entry for the store instruction in a store reorder queue, wherein the entries in the store reorder queue are executed in sequential order.

4. The computer-implemented method of claim 1 , wherein executing the plurality of instructions in the OoO window further comprises:
detecting a hazard based on the effective address without translation to real address, wherein the hazard includes one from a group of hazards consisting of a load-hit-load hazard, a store-hit-load hazard, and a load-hit-store hazard.

5. The computer-implemented method of claim 1 , wherein the EAD comprises a plurality of EAD entries, an EAD entry mapping an effective address with a corresponding ERT entry using an ERT index.

6. The computer-implemented method of claim 5 , wherein the corresponding ERT entry comprises the ERT index, the effective address, a corresponding real address, and a thread identifier.

7. The computer-implemented method of claim 1 , wherein in response to the instruction being a store instruction:
determining a real address of said store instruction mapped to the effective address from ERT table; and
issuing the store instruction using the real address of said store instruction.

Assignees

• IBM

Inventors

• Gonzalez Christopher
• Lloyd Bryan
• Sinharoy Balaram

Classifications

• G06F2212/655

  Same page detection · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title