Low Allan-Deviation oscillator

Patent metadata

Field	Value
Publication number	US-10622945-B1
Application number	US-201816046992-A
Country	US
Kind code	B1
Filing date	Jul 26, 2018
Priority date	Jul 26, 2017
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

An oscillator includes a resonator, sustaining circuit and detector circuit. The sustaining circuit receives a sense signal indicative of mechanically resonant motion of the resonator generates an amplified output signal in response. The detector circuit asserts, at a predetermined phase of the amplified output signal, one or more control signals that enable an offset-reducing operation with respect to the sustaining amplifier circuit.

First claim

What is claimed is:

1. An oscillator comprising:
a resonator;
a sustaining amplifier circuit to receive a sense signal indicative of mechanically resonant motion of the resonator and to generate an amplified output signal in response to the sense signal; and
a detector circuit to assert, at a predetermined phase of the amplified output signal, one or more control signals that enable an offset-reducing operation to reduce 1/f noise in the sustaining amplifier circuit;
wherein the amplified output signal has a frequency that is a function of the mechanically resonant motion.

2. The oscillator of claim 1 wherein the sustaining amplifier circuit comprises an input node coupled to receive the sense signal, an inverting amplifier having an input and an output and a capacitive element coupled between the input node and the input of the inverting amplifier.

3. The oscillator of claim 2 further comprising:
a first transistor switch coupled between the input of the inverting amplifier and a first voltage node;
a second transistor switch coupled between the input of the inverting amplifier and the output of the inverting amplifier; and
wherein the detector circuit to assert the one or more control signals that enable the offset-reducing operation with respect to the sustaining amplifier circuit comprises a first output to assert a first control signal that renders the first and second transistor switches into a conducting/closed state.

4. The oscillator of claim 3 further comprising a third transistor switch coupled between the input node and the capacitive element, and wherein the detector circuit to assert the one or more control signals that enable the offset-reducing operation with respect to the sustaining amplifier circuit comprises a second output to deassert a second control signal at an input of the third transistor switch to render the third transistor switch into a non-conducting/open state during an interval in which the first and second transistor switches are in the conducting/closed state.

5. The oscillator of claim 1 wherein the detector circuit to assert the one or more control signals at the predetermined phase of the amplified output signal comprises circuitry to assert the one or more control signals a first predetermined time after a zero-crossing of the amplified output signal.

6. The oscillator of claim 5 wherein the circuitry to assert the one or more control signals a first predetermined time after the zero-crossing of the amplified output signal comprises circuitry to detect the zero-crossing of the amplified output signal.

7. The oscillator of claim 6 wherein the circuitry to assert the one or more control signals a first predetermined time after the zero-crossing of the amplified output signal comprises circuitry deassert the one or more control signals signal a second predetermined time after the zero-crossing of the amplified output signal that precedes an ensuing zero-crossing of the amplified output signal.

8. The oscillator of claim 1 wherein the detector circuit to assert the one or more control signals at the predetermined phase of the amplified output signal comprises circuitry to assert a first control signal and to deassert a second control signal and thereafter to deassert the first control signal and assert the second control signal to alternately enable offset-cancellation and amplifier operation within the sustaining amplifier circuit.

9. A method of operation within a resonator-based oscillator, the method comprising:
receiving, within a sustaining amplifier circuit, a sense signal indicative of mechanically resonant motion of the resonator;
generating an amplified output signal in response to the sense signal; and
enabling an offset-reducing operation to reduce 1/f noise in the sustaining amplifier circuit at a predetermined phase of the amplified output signal;
wherein the amplified output signal has a frequency that is a function of the mechanically resonant motion.

10. The oscillator of claim 1 wherein the resonator comprises a microelectromechanical system (MEMS) resonator.

11. The oscillator of claim 10 wherein the MEMS resonator is encapsulated within a chamber in a first die and wherein said sustaining amplifier circuit and said detector circuit are formed to be part of a second die.

12. The oscillator circuit of claim 11 embodied as a package which contains both the first die and the second die.

13. The method of claim 9 wherein enabling comprises generating a control signal which asserts a state at the predetermined phase of the amplified output signal.

14. The method of claim 9 wherein enabling comprises detecting a zero crossing of the amplified output signal and controlling an enablement signal dependent on the detected zero crossing.

15. A device comprising:
a package mounting a first die and a second die;
a resonator within the first die;
a sustaining amplifier circuit and a detector circuit within the second die;
wherein the sustaining amplifier circuit is coupled to the first die to receive a sense signal indicative of mechanically resonant motion of the resonator and to generate an amplified output signal in response to the sense signal;
wherein the amplified output signal has a frequency that is a function of the mechanically resonant motion; and
wherein the detector circuit is to assert, at a predetermined phase of the amplified output signal, one or more control signals that enable an offset-reducing operation to reduce 1/f noise in the sustaining amplifier circuit.

16. The device of claim 15 wherein:
the sustaining amplifier circuit comprises an input node coupled to receive the sense signal, an inverting amplifier having an input and an output and a capacitive element coupled between the input node and the input of the inverting amplifier;
the device further comprises a first transistor switch coupled between the input of the inverting amplifier and a first voltage node, and a second transistor switch coupled between the input of the inverting amplifier and the output of the inverting amplifier; and
the detector circuit is to assert the one or more control signals that enable the offset-reducing operation with respect to the sustaining amplifier circuit comprises a first output to assert a first control signal that renders the first and second transistor switches into a conducting/closed state.

17. The device of claim 16 further comprising a third transistor switch coupled between the input node and the capacitive element, and wherein the detector circuit to assert the one or more control signals that enable the offset-reducing operation with respect to the sustaining amplifier circuit comprises a second output to deassert a second control signal at an input of the third transistor switch to render the third transistor switch into a non-conducting/open state during an interval in which the first and second transistor switches are in the conducting/closed state.

18. The device of claim 15 wherein the detector circuit to assert the one or more control signals at the predetermined phase of the amplified output signal comprises circuitry to assert the one or more control signals a first predetermined time after a zero-crossing of the amplified output signal.

19. The device of claim 15 wherein the circuitry to assert the one or more control signals a first predetermined time after the zero-crossing of the amplified output signal comprises circuitry to detect the zero-crossing of the amplified output signal.

20. The device of claim 16 w

Assignees

• Sitime Corp

Inventors

• Partridge Aaron
• Tabatabaei Sassan
• Chen Lijun
• Souri Kamran

Classifications

• H03F3/70 Primary

  Charge amplifiers · CPC title

• H03F2200/375

  Circuitry to compensate the offset being present in an amplifier · CPC title

• H03B2200/005

  including measures to switch a capacitor · CPC title

• H03B5/36 Primary

  active element in amplifier being semiconductor device ({H03B5/323, H03B5/326} , H03B5/38 take precedence) · CPC title

• H03F3/04

  with semiconductor devices only · CPC title