System and method for capacitive signal source amplifier

Patent metadata

Field	Value
Publication number	US-9455671-B2
Application number	US-201514738353-A
Country	US
Kind code	B2
Filing date	Jun 12, 2015
Priority date	Oct 31, 2012
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

In accordance with an embodiment, a system for amplifying a signal provided by a capacitive signal source includes a first voltage follower device, a second voltage follower device, and a first capacitor. The first voltage follower device includes an input terminal configured to be coupled to a first terminal of the capacitive signal source, and the second voltage follower device includes an input terminal coupled to the first output terminal of the first voltage follower device, and an output terminal coupled to a second output terminal of the first voltage follower device. Furthermore, first capacitor has a first end coupled to a first output terminal of the first voltage follower device, and a second end configured to be coupled to a second terminal of the capacitive signal source.

First claim

What is claimed is:

1. A system for amplifying a signal provided by a signal source, the system comprising:
a first voltage follower device comprising an input terminal configured to be coupled to a first terminal of the signal source;
a first capacitor comprising a first end coupled to a first output terminal of the first voltage follower device, and a second end configured to be coupled to a second terminal of the signal source; and
a second voltage follower device comprising an input terminal coupled to the first output terminal of the first voltage follower device, and an output terminal coupled to a second output terminal of the first voltage follower device.

2. The system of claim 1 , further comprising a second capacitor comprising a first end coupled to a reference node and a second end configured to be coupled to the second terminal of the signal source.

3. The system of claim 1 , wherein the first voltage follower device comprises a MOS source follower.

4. The system of claim 3 , wherein the MOS source follower is biased in a sub-threshold region.

5. The system of claim 1 , further comprising the signal source.

6. The system of claim 5 , wherein the signal source comprises a MEMS microphone.

7. The system of claim 1 , further comprising an amplification stage coupled to the first output terminal of the first voltage follower device.

8. The system of claim 1 , wherein:
the first voltage follower device comprises a MOS device;
the input terminal of the first voltage follower device comprises a gate terminal of the MOS device;
the first output terminal of the first voltage follower device comprises a source terminal of the MOS device; and
the second output terminal of the first voltage follower device comprises a drain terminal of the MOS device.

9. An amplifier for amplifying a signal provided by a signal source, the amplifier comprising:
a source follower transistor having a gate configured to be coupled to a first terminal of the signal source;
a first capacitor having a first terminal coupled to a source terminal of the source follower transistor and a second terminal configured to be coupled to a second terminal of the signal source; and
a voltage follower device comprising an input terminal coupled to a first output terminal of the source follower transistor, and an output terminal coupled to a drain terminal of the source follower transistor.

10. The amplifier of claim 9 , further comprising a second capacitor having a first terminal coupled to a reference voltage node and a second terminal configured to be coupled to the second terminal of the signal source.

11. The amplifier of claim 10 , wherein a voltage gain from the first and second terminals of the signal source to the source terminal of the source follower transistor is dependent on a ratio of a capacitance of the first capacitor and a capacitance of the second capacitor.

12. The amplifier of claim 10 , wherein a voltage gain from the first and second terminals of the signal source to the source terminal of the source follower transistor is greater than one.

13. The amplifier of claim 9 , further comprising a first bias transistor coupled between the gate of the source follower transistor and a gate reference voltage node.

14. The amplifier of claim 13 , further comprising a second bias transistor coupled between the drain terminal of the source follower transistor and a gate of the first bias transistor.

15. The amplifier of claim 14 , further comprising:
a first resistor having a first terminal coupled to the gate of the first bias transistor and a second terminal coupled to a first current source; and
a second resistor coupled between the second terminal of the first resistor and the gate reference voltage node.

16. The amplifier of claim 9 , wherein:
the source follower transistor comprises a PMOS device; and
the voltage follower device comprises a NMOS source follower transistor.

17. The amplifier of claim 9 , wherein the source follower transistor, voltage follower device, and the first capacitor are disposed on an integrated circuit.

18. The amplifier of claim 9 , wherein the source follower transistor is biased in a sub-threshold region.

19. The amplifier of claim 9 , wherein the signal source comprises a capacitive signal source.

20. The amplifier of claim 19 , wherein the capacitive signal source comprises a MEMS microphone.

21. A method of amplifying a signal provided by a signal source, the method comprising:
receiving a first signal from a first terminal of the signal source at a gate terminal of a first voltage follower device;
receiving a second signal from a second terminal of the signal source at a first capacitor coupled to a source node of the first voltage follower device;
amplifying the first and second signals, amplifying comprising applying a voltage gain based on a ratio of the first capacitor and a second capacitor coupled between the second terminal of the signal source and a reference node;
receiving a third signal from the source node of the first voltage follower device at a control terminal of a second voltage follower device; and
applying a fourth signal at an output node of the second voltage follower device to a drain node of the first voltage follower device.

22. The method of claim 21 , wherein applying the fourth signal reduces a parasitic gate-drain capacitance of the first voltage follower device.

23. The method of claim 21 , further comprising performing an analog to digital conversion on the third signal.

Assignees

• Infineon Technologies Ag

Inventors

• Kropfitsch Michael
• Ceballos Jose Luis

Classifications

• H03F2200/129

  there being a feedback over the complete amplifier · CPC title

• H03F3/187 Primary

  in integrated circuits · CPC title

• H04R3/00

  Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title