System and method for accumulating and measuring a slowly varying electrical charge

Patent metadata

Field	Value
Publication number	US-9784778-B2
Application number	US-201414778886-A
Country	US
Kind code	B2
Filing date	Dec 14, 2014
Priority date	Dec 14, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A system for measuring electrical charge, comprising a capacitance detector ( 110 ) connected to a charge integrator ( 120 ) being an operational amplifier with capacitance (Cf) feedback ( 130 ), wherein the input stage ( 121 ) of the charge integrator ( 120 ) comprises a pair of symmetrically connected complementary JFET transistors (T 1 , T 2 ), the gates of which are connected to the input of the charge integrator ( 120 ), characterized in that an n-type transistor (T 1 ) of the complementary pair of transistors (T 1 , T 2 ) has its drain connected to a voltage regulating system ( 122 ).

First claim

The invention claimed is:

1. A system for measuring electrical charge, the system comprising:
a charge integrator comprising an operational amplifier and a feedback capacitance connected between an input and output of the operational amplifier,
a capacitance detector connected to an input of the charge integrator, wherein an input stage of the charge integrator comprises a pair of symmetrically connected complementary JFET transistors, wherein gates of each transistor of the pair of the symmetrically connected complementary JFET transistors are connected to the input of the charge integrator,
and a voltage controlling system connected to a drain of an n-type transistor of the pair of the symmetrically connected complementary JFET transistors for equalizing a gate current of a p-type transistor of the pair of the symmetrically connected complementary JFET transistors with a gate current of the n-type transistor of the pair of the symmetrically connected complementary JFET transistors,
wherein the voltage controlling system is a system adapted to automatically set a drain voltage of the n-type transistor of the pair of the symmetrically connected complementary JFET transistors to a value for which a DC component of an output voltage of the charge integrator does not change.

2. The system according to claim 1 , wherein the voltage controlling system is a manually-controlled potentiometer.

3. The system according to claim 1 , wherein for a particular quiescent voltage, the gate current of the n-type transistor is lower than the gate current of the p-type transistor.

4. The system according to claim 1 , wherein the drain of the n-type transistor is powered by a power source whose current is independent of a voltage potential of the drain of the n-type transistor.

5. The system according to claim 1 , further comprising a regulated power source connected to a drain of the p-type transistor.

6. A method for measuring an electrical charge by means of a system comprising:
a charge integrator comprising an operational amplifier and a feedback capacitance connected between an input and output of the operational amplifier,
a switch for short-circuiting the feedback capacitance,
a capacitance detector connected to an input of the charge integrator, wherein an input stage of the charge integrator comprises a pair of symmetrically connected complementary JFET transistors, wherein gates of each transistor of the pair of the symmetrically connected complementary JFET transistors are connected to the input of the charge integrator,
and a voltage controlling system connected to a drain of an n-type transistor of the pair of the symmetrically connected complementary JFET transistors,
a regulated power source connected to a drain of the p-type transistor of the pair of the symmetrically connected complementary JFET transistors,
the method comprising equalizing, by means of the voltage controlling system, a gate current of the p-type transistor of the pair of the symmetrically connected complementary JFET transistors with a gate current of the n-type transistor of the pair of the symmetrically connected complementary JFET transistors and setting the regulated power source so as to set a zero output voltage of the charge integrator when the switch is closed.

Assignees

• Univ Jagiellonski

Inventors

• Sosin Zbigniew
• Adamczyk Marek
• Sosin Maciej
• Lasko Pawel

Classifications

• H03F1/523

  for amplifiers using field-effect devices (H03F1/526 takes precedence) · CPC title

• H03F3/70

  Charge amplifiers · CPC title

• G01R29/24 Primary

  Arrangements for measuring quantities of charge · CPC title

• G01R27/2605

  Measuring capacitance (capacitive sensors G01D5/24) · CPC title