Facilitation of spin-coat planarization over feature topography during substrate fabrication

US10622267B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10622267-B2
Application numberUS-201715724632-A
CountryUS
Kind codeB2
Filing dateOct 4, 2017
Priority dateOct 4, 2016
Publication dateApr 14, 2020
Grant dateApr 14, 2020

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Described herein are technologies to facilitate device fabrication, especially those that involve spin-on coatings of a substrate (e.g., wafer). More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of facilitating spin-coat planarization over feature topography during substrate fabrication, the method comprising: generating, using a data processor, a topography map for a desired pattern of features on a semiconductor substrate, the generating of the topography map being based, at least in part, on substrate patterning information related to the desired pattern of features; generating, using the data processor, a film-thickness model for predicting film thickness of a spin-on coating applied to the desired pattern of features, wherein inputs for the film-thickness model include the topography map and an estimated film thickness of the spin-on coating applied on the semiconductor substrate according to defined coating process parameters; generating, using the data processor, a film-thickness output from the film-thickness model by: assigning a plurality of grid points across the semiconductor substrate, determining a trench depth at or around each of the plurality of grid points on the semiconductor substrate based, at least in part, on the topography map, assigning a calculation distance from each of the plurality of grid points, and calculating a film thickness value for each grid point in the plurality of grid points based, at least in part, on the estimated film thickness, the trench depth proximate to each grid point, a surface area around each grid point, and film thickness values from other grid points within the calculation distance; determining, using the data processor, whether a predicted film thickness of an area of the film-thickness output falls within a defined range; and based upon that determining, either declaring the predicted film thickness of the area of the film-thickness output to be planar, or generating, using the data processor, suggested remedies to enhance planarization of the predicted film thickness of the area of the film-thickness output, wherein the suggested remedies affect the substrate fabrication. 2. The method of claim 1 , further comprising: selecting one or more of the suggested remedies; and performing the one or more selected suggested remedies. 3. A method of facilitating spin-coat planarization over feature topography during substrate fabrication, the method comprising: receiving substrate patterning information related to a desired pattern of features for a semiconductor substrate; generating, using a data processor, a topography map for the desired pattern of features based, at least in part, on the substrate patterning information; receiving data regarding a plurality of film thickness points associated with a film deposited on a patterned substrate having the desired pattern of features; generating, using the data processor, a film-thickness model for predicting film thickness for the semiconductor substrate, wherein inputs for the film-thickness model include the data of the plurality of film thickness points; and generating, using the data processor, a film-thickness output from the film-thickness model by: assigning a plurality of grid points across the semiconductor substrate, determining a trench depth at or around each of the plurality of grid points on the semiconductor substrate based, at least in part, on the topography map, assigning a calculation distance from each of the plurality of grid points, and calculating a film thickness value for each grid point in the plurality of grid points based, at least in part, on an estimated film thickness, the trench depth proximate to each grid point, a surface area around each grid point, and film thickness values from other grid points within the calculation distance. 4. The method of claim 3 , wherein the substrate patterning information comprises feature dimensions, mask tone, or film thickness measurement values. 5. The method of claim 3 , wherein the topography map comprises features varying by height, width, and distance between the features. 6. The method of claim 3 , wherein the inputs for the film-thickness model further include the estimated film thickness based, at least in part, on a blanket film thickness, a localized pattern height, a localized pattern width, and a surrounding density of features on the semi conductor substrate. 7. The method of claim 3 , wherein the plurality of film thickness data comprises thickness data of one or more films on the patterned substrate. 8. The method of claim 3 , wherein the film comprises a blanket film, a patterned film, or a treated film. 9. A method for predicting planarity of a spin coating process comprising: receiving substrate patterning information for a patterned substrate; receiving a film-thickness model for predicting film thickness for the patterned substrate, wherein inputs for the film-thickness model include an estimated thickness of a film spun onto the patterned substrate and an arrangement of features on the patterned substrate; and generating, using a data processor, a film-thickness output from the film-thickness model by: assigning a plurality of grid points across the patterned substrate, determining a trench depth at or around each of the plurality of grid points on the patterned substrate, assigning a calculation distance from each of the plurality of grid points, and calculating a film thickness value for each grid point in the plurality of grid points based, at least in part, on a blanket film thickness, the trench depth proximate to each grid point, a surface area around each grid point, and film thickness values from other grid points within the calculation distance. 10. The method of claim 9 , wherein the estimated thickness is based, at least in part, on the blanket film thickness and topography of the patterned substrate. 11. The method of claim 9 , wherein the arrangement of features is based, at least in part, on one or more of the following: feature depth, feature width, or feature surface area at different locations across the patterned substrate. 12. The method of claim 9 further comprising: comparing the film-thickness output to a predetermined specification; and adjusting one or more process conditions based, at least in part, on the comparing of the film-thickness output and the predetermined specification. 13. The method of claim 12 wherein the one or more process conditions include one or more of the following: spin speed for the film being deposited on the patterned substrate, focus or dose of a lithography process used to pattern the patterned substrate, etch time, or etch power. 14. The method of claim 9 further comprising: comparing the film-thickness output to a predetermined specification; adjusting one or more process targets based, at least in part, on the comparing of the film-thickness output with the predetermined specification. 15. The method of claim 14 wherein the one or more process targets include one or more of the following: deposition thickness, trench depth, film non-uniformity. 16. The method of claim 9 further comprising: comparing the film-thickness output to a predetermined specification; and adjusting one or more design conditions based, at least in part, on the comparing of the film-thickness output and the predetermined specification. 17. The method of claim 16 wherein the design conditions include one or more of the following: device layout, dummy fill layout, mask layout, or other conditions that impact pattern density on the patterned substrate. 18. The method of claim 9 , wherein the film-thickness model includes thickness data of one or more films on t

Assignees

Inventors

Classifications

  • Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

  • the removal being chemical etching · CPC title

  • H10P74/23Primary

    characterised by multiple measurements, corrections, marking or sorting processes · CPC title

  • Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

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What does patent US10622267B2 cover?
Described herein are technologies to facilitate device fabrication, especially those that involve spin-on coatings of a substrate (e.g., wafer). More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit th…
Who is the assignee on this patent?
Tokyo Electron Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/6342. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 14 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).