Methods of identifying space within integrated circuit structure as mandrel space or non-mandrel space

Patent metadata

Field	Value
Publication number	US-10622266-B2
Application number	US-201715478441-A
Country	US
Kind code	B2
Filing date	Apr 4, 2017
Priority date	Apr 4, 2017
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

The disclosure is directed to methods of identifying a space within an integrated circuit structure as a mandrel space or a non-mandrel space. One method may include: identifying a space between freestanding spacers as being one of: a former mandrel space created by removal of a mandrel from between the freestanding spacers or a non-mandrel space between adjacent mandrels prior to removal of the mandrel, based on a line width roughness of the space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space.

First claim

What is claimed is:

1. A method comprising:
identifying a space between freestanding spacers as being one of: a mandrel space created by removal of a mandrel from between the freestanding spacers or a non-mandrel space between adjacent mandrels prior to removal of the mandrel, based on a line width roughness of the space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space, and wherein the identifying further includes:
calculating the line width roughness of the space and a line width roughness of another, adjacent space positioned alongside one of the freestanding spacers,
determining whether the line width roughness of the space is less than the line width roughness of the another, adjacent space,
in response to the line width roughness of the space being less than the line width roughness of the another, adjacent space, identifying the space as the mandrel space, and
in response to the line width roughness of the space not being less than the line width roughness of the another, adjacent space, identifying the space as the non-mandrel space.

2. The method of claim 1 , further comprising:
determining the line width roughness of the space using at least one of: a scanning electron microscope (SEM), an atomic force microscope (AFM), or an optical critical dimension (OCD) tool.

3. The method of claim 1 , wherein the space includes a length of approximately 200 nanometers (nm) to approximately 10,000 nm.

4. The method of claim 1 , further comprising:
adjusting one of a depositing or an etching of a spacer material of additional freestanding spacers in a subsequently fabricated integrated circuit structure based on the identifying.

5. The method of claim 1 , wherein the line width roughness is calculated by the following equation:
LWR=3√{square root over (σ xR 2 +σ xL 2 −2 cov( x L ,x R ))}

wherein LWR represents the line width roughness, σ xR represents standard deviation of the line edge roughness of the right edge, σ xL represents standard deviation of the line edge roughness of the left edge, and cov(x L , x R ) represents is the covariance between the left and right edge.

6. The method of claim 1 , wherein the identifying is performed by a program product stored on a computer readable medium.

7. A method comprising:
providing an integrated circuit structure having:
a first mandrel over a substrate and a second mandrel over the substrate laterally adjacent to the first mandrel;
a pair of spacers on opposing sides of each mandrel over the substrate; and
a non-mandrel space between adjacent spacers of the first and second mandrels,

removing each mandrel to expose the substrate thereunder, thereby defining a mandrel space between the pair of spacers of each mandrel;
calculating a line width roughness of each of the non-mandrel space and the mandrel space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space; and
identifying which space constitutes the non-mandrel space between the adjacent spacers and the mandrel space based on the line width roughness of the non-mandrel space and the mandrel space, wherein the identifying further includes:
determining whether the line width roughness of a selected space is less than the line width roughness of another, adjacent space,
in response to the line width roughness of the selected space being less than the line width roughness of the another, adjacent space, identifying the selected space as the mandrel space, and
in response to the line width roughness of the selected space not being less than the line width roughness of the another, adjacent space, identifying the selected space as the non-mandrel space.

8. The method of claim 7 , wherein the measuring of the line width roughness of each of the non-mandrel space and the mandrel space is accomplished using at least one of: a scanning electron microscope (SEM), an atomic force microscope (AFM), or an optical critical dimension (OCD) tool.

9. The method of claim 7 , wherein each of the non-mandrel space and the mandrel space includes a length of approximately 200 nanometers (nm) to approximately 10,000 nm.

10. The method of claim 7 , further comprising:
adjusting one of a depositing or an etching of a spacer material of additional spacers in a subsequently fabricated integrated circuit structure based on the identifying.

11. The method of claim 7 , wherein the line width roughness is calculated by the following equation:
LWR=3√{square root over (σ xR 2 +σ xL 2 −2 cov( x L ,x R ))}

wherein LWR represents the line width roughness, σ xR represents standard deviation of the line edge roughness of the right edge, σ xL represents standard deviation of the line edge roughness of the left edge, and cov(x L , x R ) represents is the covariance between the left and right edge.

Assignees

• Globalfoundries Inc

Inventors

• Verduijn Erik A
• Beique Genevieve
• Licausi Nicholas V
• Sun Lei
• Goodwin Francis G

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H01L22/20 Primary

  Electricity · mapped topic

• H01L22/12

  Electricity · mapped topic