Thin recon interposer package without TSV for fine input/output pitch fan-out

Patent metadata

Field	Value
Publication number	US-10615110-B2
Application number	US-201816017068-A
Country	US
Kind code	B2
Filing date	Jun 25, 2018
Priority date	Jul 9, 2015
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer. The circuit assembly further includes an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps and an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly.

First claim

What is claimed is:

1. A circuit assembly, comprising:
a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps;
an oxide layer disposed directly on, and in contact with, the silicon pad layer;
an interposer dielectric layer disposed on the oxide layer, the interposer dielectric layer including a plurality of routing traces that connect a top surface of the interposer dielectric layer to a bottom surface of the interposer dielectric layer; and
an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps.

2. The circuit assembly of claim 1 , wherein the silicon pad layer, the oxide layer, and the interposer dielectric layer form an interposer, and wherein an encapsulating material covers sidewalls of the interposer.

3. The circuit assembly of claim 2 , wherein the encapsulating material extends below the interposer so that the interposer is recessed in the encapsulating material to form an encapsulating material skirt.

4. The circuit assembly of claim 1 , further comprising:
a heat spreader attached to at least one surface of the IC die.

5. The circuit assembly of claim 1 , wherein the IC die is completely encased in an encapsulating material.

6. The circuit assembly of claim 1 , further comprising an underfill layer deposited between a bottom surface of the IC die and the top surface of the interposer dielectric layer, wherein the underfill layer encapsulates the plurality of IC bumps.

7. The circuit assembly of claim 1 , further comprising a package substrate attached to the silicon pad layer by the plurality of bumps at a top surface of the package substrate.

8. The circuit assembly of claim 1 , further comprising a second IC die attached to the top surface of the interposer dielectric layer and electrically coupled with the IC die through a second plurality of routing traces disposed in the interposer dielectric layer.

9. A circuit assembly, comprising:
a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps;
an interposer dielectric layer disposed on the silicon pad layer, the interposer dielectric layer including a plurality of routing traces that connect a top surface of the interposer dielectric layer to a bottom surface of the interposer dielectric layer;
an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps; and
a heat spreader attached to at least one surface of the IC die.

10. The circuit assembly of claim 9 , further comprising a package substrate attached to the silicon pad layer by the plurality of bumps at a top surface of the package substrate.

11. The circuit assembly of claim 9 , wherein the silicon pad layer and the interposer dielectric layer form an interposer, and wherein an encapsulating material covers sidewalls of the interposer.

12. The circuit assembly of claim 11 , wherein the encapsulating material extends below the interposer so that the interposer is recessed in the encapsulating material to form an encapsulating material skirt.

13. The circuit assembly of claim 9 , further comprising a second IC die attached to the top surface of the interposer dielectric layer and electrically coupled with the IC die through a second plurality of routing traces disposed in the interposer dielectric layer.

14. The circuit assembly of claim 9 , further comprising an underfill layer deposited between a bottom surface of the silicon pad layer and a top surface of a package substrate, wherein the underfill layer encapsulates the plurality of bumps.

15. A circuit assembly, comprising:
a dielectric layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps;
an interposer dielectric layer disposed on the dielectric layer, the interposer dielectric layer including a plurality of routing traces that connect a top surface of the interposer dielectric layer to a bottom surface of the interposer dielectric layer; and
an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps, wherein the interposer dielectric layer and the dielectric layer are formed from the same material.

16. The circuit assembly of claim 15 , wherein the dielectric layer and the interposer dielectric layer form an interposer, further comprising an encapsulating material covers sidewalls of the interposer.

17. The circuit assembly of claim 16 , wherein the encapsulating material extends below the interposer so that the interposer is recessed in the encapsulating material.

18. The circuit assembly of claim 15 , further comprising a second IC die attached to the top surface of the interposer dielectric layer and electrically coupled with the IC die through a second plurality of routing traces disposed in the interposer dielectric layer.

19. The circuit assembly of claim 15 , further comprising a package substrate attached to a silicon pad layer by the plurality of bumps at a top surface of the package substrate.

20. The circuit assembly of claim 15 , further comprising an underfill layer deposited between a bottom surface of a silicon pad layer and a top surface of a package substrate, wherein the underfill layer encapsulates the plurality of bumps.

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Zhao Sam Ziqun
• Karikalan Sam Komarapalayam
• Law Edward
• Khan Rezaur Rahman
• Vorenkamp Pieter

Classifications

• H01L25/0655

  Electricity · mapped topic

• H01L2924/00012

  Electricity · mapped topic

• H01L2224/97

  Electricity · mapped topic

• H01L23/49838 Primary

  Electricity · mapped topic

• H01L23/3114

  Electricity · mapped topic