Thin recon interposer package without TSV for fine input/output pitch fan-out

Patent metadata

Field	Value
Publication number	US-10008439-B2
Application number	US-201615205991-A
Country	US
Kind code	B2
Filing date	Jul 8, 2016
Priority date	Jul 9, 2015
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer. The circuit assembly further includes an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps and an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly.

First claim

What is claimed is:

1. A circuit assembly, comprising:
a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps;
an oxide layer disposed directly on, and in contact with, the silicon pad layer;
an interposer dielectric layer disposed on the oxide layer, the interposer dielectric layer including a plurality of routing traces that connect a top surface of the interposer dielectric layer to a bottom surface of the interposer dielectric layer;
an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps; and
an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly.

2. The circuit assembly of claim 1 , wherein the silicon pad layer, the oxide layer, and the interposer dielectric layer form an interposer, and wherein the encapsulating material covers sidewalls of the interposer.

3. The circuit assembly of claim 2 , wherein the encapsulating material extends below the interposer so that the interposer is recessed in the encapsulating material to form an encapsulating material skirt.

4. The circuit assembly of claim 1 , wherein the IC die is completely encased in the encapsulating material.

5. The circuit assembly of claim 1 , further comprising an underfill layer deposited between a bottom surface of the IC die and the top surface of the interposer dielectric layer, wherein the underfill layer encapsulates the plurality of IC bumps.

6. The circuit assembly of claim 1 , further comprising a package substrate attached to the silicon pad layer by the plurality of bumps at a top surface of the package substrate.

7. The circuit assembly of claim 1 , further comprising a second IC die attached to the top surface of the interposer dielectric layer and electrically coupled with the IC die through a second plurality of routing traces disposed in the interposer dielectric layer.

8. A circuit assembly, comprising:
a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps;
an oxide layer disposed on the silicon pad layer;
an interposer dielectric layer disposed on the oxide layer, the interposer dielectric layer including a plurality of routing traces that connect a top surface of the interposer dielectric layer to a bottom surface of the interposer dielectric layer;
an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps;
an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly, wherein at least one surface of the IC die is exposed through the encapsulating material; and
a heat spreader attached to the at least one surface of the IC die exposed through the encapsulating material.

9. A circuit assembly, comprising:
a dielectric layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps;
an interposer dielectric layer disposed on the dielectric layer, the interposer dielectric layer including a plurality of routing traces that connect a top surface of the interposer dielectric layer to a bottom surface of the interposer dielectric layer;
an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps; and
an encapsulating material encapsulating at least a portion of the dielectric layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly,
wherein the interposer dielectric layer and the dielectric layer are formed from the same material.

10. The circuit assembly of claim 8 , further comprising an underfill layer deposited between a bottom surface of the IC die and the top surface of the interposer dielectric layer, wherein the underfill layer encapsulates the plurality of IC bumps.

11. The circuit assembly of claim 8 , further comprising a package substrate attached to the silicon pad layer by the plurality of bumps at a top surface of the package substrate.

12. The circuit assembly of claim 8 , further comprising a second IC die attached to the top surface of the interposer dielectric layer and electrically coupled with the IC die through a second plurality of routing traces disposed in the interposer dielectric layer.

13. A circuit assembly, comprising:
a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps;
an interposer dielectric layer disposed on the silicon pad layer, the interposer dielectric layer including a plurality of routing traces that connect a top surface of the interposer dielectric layer to a bottom surface of the interposer dielectric layer;
an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps;
an encapsulating material encapsulating at least a portion of the silicon pad layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly, wherein at least one surface of the IC die is exposed through the encapsulating material; and
a heat spreader attached to the at least one surface of the IC die exposed through the encapsulating material.

14. The circuit assembly of claim 13 , wherein the silicon pad layer and the interposer dielectric layer form an interposer, and wherein the encapsulating material covers sidewalk of the interposer.

15. The circuit assembly of claim 14 , wherein the encapsulating material extends below the interposer so that the interposer is recessed in the encapsulating material to form an encapsulating material skirt.

16. The circuit assembly of claim 13 , further comprising a second IC die attached to the top surface of the interposer dielectric layer and electrically coupled with the IC die through a second plurality of routing traces disposed in the interposer dielectric layer.

17. The circuit assembly of claim 13 , further comprising an underfill′ layer deposited between a bottom surface of the silicon pad layer and a top surface of a package substrate, wherein the underfill layer encapsulates the plurality of bumps.

18. The circuit assembly of claim 9 , further comprising a second IC die attached to the top surface of the interposer dielectric layer and electrically coupled with the IC die through a second plurality of routing traces disposed in the interposer dielectric layer.

19. The circuit assembly of claim 9 , wherein the dielectric layer and the interposer dielectric layer form an interposer, and wherein the encapsulating material covers sidewalls of the interposer.

20. The circuit assembly of claim 19 , wherein the encapsulating material extends below the interposer so that the interposer is recessed in the encapsulating material.

Assignees

• Avago Technologies General Ip

Inventors

• Zhao Sam Ziqun
• Karikalan Sam Komarapalayam
• Law Edward
• Khan Rezaur Rahman
• Vorenkamp Pieter

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/0198

  batch processes · CPC title