Short detection and inversion

Patent metadata

Field	Value
Publication number	US-10614907-B2
Application number	US-201916242892-A
Country	US
Kind code	B2
Filing date	Jan 8, 2019
Priority date	Sep 30, 2014
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

First claim

What is claimed is:

1. A memory device comprising:
a memory array including a plurality of bit cells, wherein each bit cell of the plurality of bit cells is configured to switch between a first state and a second state;
a sense amplifier configured to read data associated with a state of each bit cell of the plurality of bit cells; and
a detection circuit configured to receive the read data from the sense amplifier, the detection circuit comprising a plurality of detector components, wherein each detector component is configured to identify at least one bit cell of the plurality of bit cells fixed in one of the first or second states, wherein each detector component comprises a first logic device and a second logic device, wherein an output of the first logic device is a first input to the second logic device, and wherein an output of the second logic device is configured to indicate whether the at least one bit cell of the plurality of bit cells is fixed in one of the first or second states.

2. The memory device as recited in claim 1 , wherein the fixed state of the at least one bit cell is in one of a high resistive state or a low resistive state.

3. The memory device as recited in claim 1 , wherein the first logic device is a XNOR logic device and the second logic device is an AND logic device.

4. The memory device as recited in claim 1 , wherein the detection circuit is configured to identify the at least one bit cell based at least in part on a voltage generated by a reference resistance.

5. The memory device as recited in claim 4 , wherein the detection circuit is configured to identify the at least one bit cell based at least in part on a sample voltage.

6. The memory device as recited in claim 1 , wherein the detection circuit is further configured to receive error data from an error correction component, and wherein the error data is a second input to the second logic device.

7. The memory device as recited in claim 1 , wherein the detection circuit is further configured to receive the read data from the sense amplifier as a first input to the first logic device.

8. The memory device as recited in claim 1 , wherein the detection circuit is further configured to receive reference data as a second input to the first logic device, and wherein the reference data is indicative of an expected fixed state of the at least one bit cell.

9. A method comprising:
receiving a plurality of data bits to be stored in a memory array, wherein the memory array includes a plurality of bit cells, and wherein each bit cell of the plurality of bit cells is configured to switch between a first state and a second state;
identifying a first bit cell of the plurality of bit cells fixed in one of the first or second states;
determining a state of the first bit cell;
identifying a first data bit of the plurality of data bits to be stored in the first bit cell;
determining a state of the first data bit;
determining that the state of the first bit cell and the state of the first data bit are different; and
in response to determining that the state of the first bit cell and the state of the first data bit are different, providing an output signal indicating that the first bit cell of the plurality of bit cells is fixed in one of the first or second states.

10. The method as recited in claim 9 , wherein the state of the first data bit is a high state and the state of the first bit cell is a low state.

11. The method as recited in claim 9 , wherein the state of the first data bit is a low state and the state of the first bit cell is a high state.

12. The method as recited in claim 9 , wherein the first bit cell is identified based at least in part on a reference resistance.

13. The method as recited in claim 9 , wherein the first bit cell is identified based at least in part on a voltage reference.

14. A memory device comprising:
a memory array including a plurality of bit cells, wherein each bit cell of the plurality of bit cells is configured to switch between a first state and a second state;
a sense amplifier configured to read data associated with a state of each bit cell of the plurality of bit cells;
an error correction component configured to generate error data based on the data stored in each bit cell of the plurality of bit cells; and
a detection circuit configured to receive the read data from the sense amplifier and the error data from the error correction component, the detection circuit comprising a plurality of detector components, wherein each detector component is configured to identify at least one bit cell of the plurality of bit cells fixed in one of the first or second states, wherein each detector component comprises a first logic device and a second logic device, wherein an output of the first logic device is a first input to the second logic device, and wherein an output of the second logic device is configured to indicate whether the at least one bit cell of the plurality of bit cells is fixed in one of the first or second states.

15. The memory device as recited in claim 14 , wherein the fixed state of the at least one bit cell is in one of a high resistive state or a low resistive state.

16. The memory device as recited in claim 14 , wherein the first logic device is a XNOR logic device.

17. The memory device as recited in claim 14 , wherein the second logic device is an AND logic device.

18. The memory device as recited in claim 14 , wherein the detection circuit is configured to identify the at least one bit cell based at least in part on a voltage generated by a reference resistance.

19. The memory device as recited in claim 14 , wherein the detection circuit is configured to identify the at least one bit cell based at least in part on a sample voltage.

20. The memory device as recited in claim 14 , wherein the read data is an input to the first logic device, and wherein the error data is an input to the second logic device.

Assignees

• Everspin Technologies Inc

Inventors

• Andre Thomas
• Slaughter Jon
• Houssameddine Dimitri
• Alam Syed M

Classifications

• G11C29/50 Primary

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G06F11/08

  Error detection or correction by redundancy in data representation, e.g. by using checking codes · CPC title