Short detection and inversion

Patent metadata

Field	Value
Publication number	US-9502089-B2
Application number	US-201414502287-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Sep 30, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

First claim

What is claimed is:

1. A memory device comprising:
a memory array having a plurality of bit cells;
a short detection component configured to identify at least one shorted bit cell of the plurality of bit cells of the memory array; and
an inversion component configured to:
receive a plurality of data bits;
determine a state of the at least one shorted bit cell;
determine that the state of the at least one shorted bit cell differs from a state of a data bit of the plurality of data bits to be stored in the shorted bit cell; and
invert, in response to determining that the state of the at least one shorted bit cell differs from the state of the data bit, the plurality of data bits.

2. The memory device as recited in claim 1 , wherein the plurality of bit cells are associated with a particular error correction code (ECC) word of the memory array.

3. The memory device as recited in claim 1 , wherein:
the at least one shorted bit cell includes at least three shorted bit cells; and
the inversion component is configured to determine a majority state associated with the data bits to be stored in the at least three shorted bit cells, and to invert a state of each of the plurality of data bits based at least in part on the majority state.

4. The memory device as recited in claim 1 , wherein the short detection component is configured to identify the at least one shorted bit cell based at least in part on a voltage generated by a referenced resistance.

5. The memory device as recited in claim 4 , wherein the short detection component is configured to identify the at least one shorted bit cell based at least in part on a sampled voltage.

6. The memory device as recited in claim 1 , wherein the inversion component is configured to invert the plurality of data bits to be stored in the memory array based at least in part on a state of the at least one shorted bit cell.

7. The memory device as recited in claim 1 , wherein the inversion component is configured to invert the plurality of data bits to be stored in the memory array based at least in part a number of matches identified by comparing a fixed state of each of the at least one shorted bit cell and the state of the data bit of the plurality of data bits to be stored in each of the at least one shorted bit cell.

8. The memory device as recited in claim 1 , further comprising an error correction component configured to provide error data to the detection component and wherein the detection component is configured to identify the at least one shorted bit based at least in part on the error data.

9. The memory device as recited in claim 1 , further comprising a sense amplifier component configured to provide read data associated with a state of each of the plurality of bit cells to the detection component and wherein the detection component is configured to identify the at least one shorted bit based at least in part on the read data.

10. The memory device as recited in claim 1 , further comprising a sense amplifier component configured to provide read data associated with a state of each of the plurality of bit cells to the inversion component and wherein the detection component is configured to identify the at least one shorted bit based at least in part on the read data.

11. A method comprising:
receiving a plurality of data bits to be stored in a memory array;
identifying a first shorted bit cell of the memory array;
determining a state associated with the first shorted bit cell;
identifying a first data bit of the plurality of data bits to be stored in the first shorted bit cell;
determining a state associated with the first data bit;
determining that the state of the first shorted bit and the state of the first data bit are different;
in response to determining the state of the first shorted bit and the state of the first data bit are different, inverting the plurality of data bits; and
storing the plurality of inverted data bits in the memory array.

12. The method as recited in claim 11 , wherein the state of the first data bit is a high state and the state of the first shorted bit is a low state.

13. The method as recited in claim 11 , wherein the state of the first data bit is a low state and the state of the first shorted bit is a high state.

14. The method as recited in claim 11 , wherein the first shorted bit cell is identified based at least in part on a reference resistance.

15. The method as recited in claim 11 , wherein the first shorted bit cell is identified based at least in part on a voltage reference.

16. The method as recited in claim 11 , further comprising preventing a write voltage from being applied to a second shorted bit cell when the state of the first data bit differs from a state of a second data bit, the second data bit to be stored in the second shorted bit cell.

17. A method comprising:
receiving data to be stored in a memory array, the data including a plurality of data bits, a first portion of the plurality of data bits having a first state and a second portion of the plurality of data bits having a second state;
determining that at least one bit cell of the memory array is shorted;
determining a state of a data bit of the plurality of data bits, the data bit to be stored in the at least one bit cell;
storing the plurality of data bits in the memory array when the state of the data bit is the first state;
inverting a state of each of the plurality of data bits when the state of the data bit to be stored in the at least one bit cell is the second state; and
storing the plurality of inverted data bits in the memory array when the state of the data bit to be stored in the at least one bit cell is the second state.

18. The method as recited in claim 17 , further comprising setting an inversion bit to the second state when the state of the data bit to be stored in the at least one bit cell is the second state.

19. The method as recited in claim 17 , wherein the at least one shorted bit cell is a differential bit cell.

20. The method as recited in claim 17 , further comprising:
identifying a majority state associated with the data when the state of the data bit to be stored in the bit cell is the first state; and
inverting the data when the majority state is the second state, prior to storing the data in the memory array.

Assignees

• Everspin Technologies Inc

Inventors

• Andre Thomas
• Slaughter Jon
• Houssameddine Dimitri
• Alam Syed M

Classifications

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G11C29/50 Primary

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G06F11/08

  Error detection or correction by redundancy in data representation, e.g. by using checking codes · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C2029/0411

  Online error correction · CPC title