Short detection and inversion

Patent metadata

Field	Value
Publication number	US-10199122-B2
Application number	US-201715852678-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Sep 30, 2014
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

First claim

What is claimed is:

1. A memory device comprising:
a memory array including a plurality of bit cells, wherein each bit cell of the plurality of bit cells is configured to switch between a first state and a second state;
a sense amplifier configured to read data associated with a state of each of the plurality of bit cells;
a detection circuit configured to receive the read data from the sense amplifier and identify at least one bit cell of the plurality of bit cells fixed in one of the first or second states; and
an inversion circuit configured to:
determine that a state of a data bit to be stored in the at least one bit cell differs from the fixed state of the at least one bit cell;
invert the data bit, in response to determining that the state of the data differs from the fixed state of the at least one bit cell; and
set an inversion bit, in response to inverting the data bit.

2. The memory device as recited in claim 1 , wherein the fixed state of the at least one bit cell is in one of a high resistive state or a low resistive state.

3. The memory device as recited in claim 1 , wherein:
the at least one bit cell includes at least three bit cells; and
the inversion circuit is further configured to:
determine a majority state associated with a plurality of data bits to be stored in the at least three bit cells, and
invert a state of each of the plurality of data bits based at least in part on the majority state determination.

4. The memory device as recited in claim 1 , wherein the detection circuit is configured to identify the at least one bit cell based at least in part on a voltage generated by a reference resistance.

5. The memory device as recited in claim 4 , wherein the detection circuit is configured to identify the at least one bit cell based at least in part on a sample voltage.

6. The memory device as recited in claim 1 , wherein the inversion circuit is configured to invert a plurality of data bits to be stored in the memory array based at least in part on a state of the at least one bit cell.

7. The memory device as recited in claim 1 , wherein the inversion circuit is configured to invert a plurality of data bits to be stored in the memory array based at least in part on a number of matches identified by comparing a fixed state of each of the at least one bit cell and the state of the data bit of the plurality of data bits to be stored in each of the at least one bit cell.

8. The memory device as recited in claim 1 , further comprising an error correction circuit configured to provide error data to the detection circuit, and wherein the detection circuit is configured to identify the at least one bit cell based at least in part on the error data.

9. The memory device as recited in claim 1 , wherein the sense amplifier is configured to provide the read data to the inversion circuit, and wherein the detection circuit is configured to identify the at least one bit cell based at least in part on the read data.

10. A method comprising:
receiving a plurality of data bits to be stored in a memory array, wherein the memory array includes a plurality of bit cells, and wherein each bit cell of the plurality of bit cells is configured to switch between a first state and a second state;
identifying a first bit cell of the plurality of bit cells fixed in one of the first or second states;
determining a state of the first bit cell;
identifying a first data bit of the plurality of data bits to be stored in the first bit cell;
determining a state of the first data bit;
determining that the state of the first bit cell and the state of the first data bit are different;
in response to determining that the state of the first bit cell and the state of the first data bit are different, inverting the plurality of data bits and setting an inversion bit; and
storing the plurality of inverted data bits and the inversion bit in the memory array.

11. The method as recited in claim 10 , wherein the state of the first data bit is a high state and the state of the first bit cell is a low state.

12. The method as recited in claim 10 , wherein the state of the first data bit is a low state and the state of the first bit cell is a high state.

13. The method as recited in claim 10 , wherein the first bit cell is identified based at least in part on a reference resistance.

14. The method as recited in claim 10 , wherein the first bit cell is identified based at least in part on a voltage reference.

15. The method as recited in claim 10 , further comprising preventing a write voltage from being applied to a second bit cell when the state of the first data bit differs from a state of a second data bit, the second data bit to be stored in the second bit cell.

16. A method comprising:
receiving data to be stored in a memory array, the data including a plurality of data bits, a first portion of the plurality of data bits having a first state, and a second portion of the plurality of data bits having a second state;
identifying at least one fixed-state bit cell in the memory array;
identifying a data bit targeted for storage in the at least one fixed-state bit cell;
determining a state of the data bit; and
storing the plurality of data bits in the memory array, wherein the step of storing the plurality of data bits includes:
(i) storing the plurality of data bits when the state of the data bit is the first state; or
(ii) inverting a state of each of the plurality of data bits, setting an inversion bit, and storing the plurality of inverted data bits and the inversion bit in the memory array when the state of the data bit is the second state.

17. The method as recited in claim 16 , wherein the at least one fixed-state bit cell is a differential bit cell.

18. The method as recited in claim 16 , further comprising:
identifying a majority state associated with the data when the state of the data bit to be stored in the fixed-state bit cell is the first state; and
inverting the data when the majority state is the second state, prior to storing the data in the memory array.

19. The method as recited in claim 16 , wherein the at least one fixed-state bit cell is identified based at least in part on a reference resistance.

20. The method as recited in claim 16 , wherein the at least one fixed-state bit cell is identified based at least in part on a voltage reference.

Assignees

• Everspin Technologies Inc
• Everspin Technologies Inc

Inventors

• Andre Thomas
• Slaughter Jon
• Houssameddine Dimitri
• Alam Syed M

Classifications

• G11C2029/0411

  Online error correction · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G11C29/50 Primary

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G06F11/08

  Error detection or correction by redundancy in data representation, e.g. by using checking codes · CPC title