Performance power optimized full adder

Patent metadata

Field	Value
Publication number	US-10613829-B2
Application number	US-201815982987-A
Country	US
Kind code	B2
Filing date	May 17, 2018
Priority date	May 17, 2018
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.

First claim

We claim:

1. A sum logic circuit for a full adder for adding a first input signal, a second input signal, and a carry-in signal, the sum logic circuit comprising:
an exclusive not-OR (XNOR) gate configured to XNOR the first input signal with the second input signal to form an XNOR signal;
a first inverter configured to invert the XNOR signal to form an exclusive OR (XOR) signal;
a second inverter configured to invert the carry-in signal to form a complement carry-in signal;
a first AND gate configured to AND the complement carry-in signal and the XNOR signal to form a first AND signal;
a second AND gate configured to AND the carry-in signal and the XOR signal to form a second AND signal; and
a not-OR (NOR) gate configured to NOR the first AND signal and the second AND signal to form a sum signal.

2. A sum logic circuit for a full adder for adding a first input signal, a second input signal, and a carry-in signal to form a sum signal, the sum logic circuit comprising:
an exclusive not-OR (XNOR) gate configured to XNOR the first input signal with the second input signal to form an XNOR signal;
a first inverter configured to invert the XNOR signal to form an exclusive OR (XOR) signal;
a second inverter configured to invert the carry-in signal to form a complement carry-in signal;
a plurality of logic gates configured to process the carry-in signal, the complement carry-in signal, the XNOR signal, and the XOR signal to produce a sum signal on a sum node;
the plurality of logic gates comprising a first switch coupled between the sum signal node and a power supply node for carrying a power supply voltage, wherein the first switch is configured to close responsive to the complement carry-in signal and the XOR signal both being discharged.

3. The sum logic circuit of claim 2 , wherein the plurality of logic gates further comprises:
a second switch coupled between the sum signal node and the power supply node, wherein the second switch is configured to close responsive to the XNOR signal and the carry-in signal both being discharged.

4. The sum logic circuit of claim 3 , wherein the first switch comprises:
a first p-type metal oxide semiconductor (PMOS) transistor; and
a second PMOS transistor arranged in series with the first PMOS transistor to form a first series of PMOS transistors coupled between the sum signal node and the power supply node.

5. The sum logic circuit of claim 4 , wherein the second switch comprises:
a third PMOS transistor arranged in series with a fourth PMOS transistor to form a second series of PMOS transistors coupled between the sum signal node and the power supply node.

6. The sum logic circuit of claim 3 , wherein the plurality of logic gates further comprises:
a third switch coupled between the sum signal node and ground, wherein the third switch is configured to close responsive to the XOR signal and the carry-in signal both being charged to the power supply voltage.

7. The sum logic circuit of claim 6 , wherein the plurality of logic gate further comprises:
a fourth switch coupled between the sum signal node and ground, wherein the fourth switch is configured to close responsive to the XNOR signal and the complement carry-in signal both being charged to the power supply voltage.

8. The sum logic circuit of claim 7 , wherein the third switch comprises:
a first n-type metal oxide semiconductor (NMOS) transistor arranged in series with a second NMOS transistor to form a first series of NMOS transistors coupled between the sum signal node and ground.

9. The sum logic circuit of claim 8 , wherein the fourth switch comprises:
a third NMOS transistor arranged in series with a fourth NMOS transistor to form a second series of NMOS transistors coupled between the sum signal node and ground.

10. The sum logic circuit of claim 1 , further comprising a carry-out logic circuit for the full adder, wherein the carry-out logic circuit comprises a plurality of AND gates and a not-OR (NOR) gate.

11. A method for forming a sum signal for a full adder, comprising:
exclusive not-ORing (XNORing) a pair of input signals for the full adder in an XNOR gate to form an XNOR signal;
inverting the XNOR signal in an inverter to form an XOR signal;
ANDing the complement of the carry-in signal and the XNOR signal in a first AND gate to form a first AND output signal;
ANDing the carry-in signal and the XOR signal in a second AND gate to form a second AND output signal; and
not-ORing the first AND output signal and the second AND output signal in a NOR gate to form the sum signal.

Assignees

• Qualcomm Inc

Inventors

• Srivastava Manish
• Dhakshinamoorthy Esakkimuthu
• Gupta Neha

Classifications

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/212

  using bipolar transistors · CPC title

• G06F7/5016

  forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• G06F7/503 Primary

  using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal · CPC title