Full adder circuit

Patent metadata

Field	Value
Publication number	US-9239703-B2
Application number	US-201314085396-A
Country	US
Kind code	B2
Filing date	Nov 20, 2013
Priority date	Jul 10, 2013
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A full adder circuit includes a first logical operation unit suitable for outputting an inverse of the second input signal and a first output signal corresponding to either a second input signal or the inverse of the second input signal in response to a first input signal, a second logical operation unit suitable for outputting an inverse of the first output signal and a sum signal corresponding to either the first output signal or the inverse of the first output signal in response to a carry input signal, and a third logical operation unit suitable for outputting a carry output signal in response to the inverse of the second input signal, the first output signal, the inverse of the first output signal, and the sum signal.

First claim

What is claimed is:

1. A full adder circuit, comprising:
a first logical operation unit suitable for outputting an inverse of the second input signal and a first output signal corresponding to either a second input signal or the inverse of the second input signal in response to a first input signal;
a second logical operation unit suitable for outputting an inverse of the first output signal and a sum signal corresponding to either the first output signal or the inverse of the first output signal in response to a carry input signal; and
a third logical operation unit suitable for outputting a carry output signal in response to the inverse of the second input signal, the first output signal, the inverse of the first output signal, and the sum signal.

2. The full adder circuit of claim 1 , wherein the first logical operation unit is suitable for performing XOR operation for the first input signal and the second input signal.

3. The full adder circuit of claim 1 , wherein the first logical operation unit includes:
a first inverter suitable for inverting the first input signal to output the inverse of the first input signal;
a second inverter suitable for inverting the second input signal to output the inverse of the second input signal;
a first transmission gate suitable for outputting the second input signal as the first output signal in response to the first input signal and the inverse of the first input signal; and
a second transmission gate suitable for outputting the inverse of the second input signal as the first output signal in response to the first input signal and the inverse of the first input signal.

4. The full adder circuit of claim 1 , wherein the second logical operation unit is suitable for performing XOR operation for the first output signal and the carry input signal.

5. The full adder circuit of claim 1 , wherein the second logical operation unit includes:
a third inverter suitable for inverting the carry input signal to output the inverse of the carry input signal;
a fourth inverter suitable for inverting the first output signal to output the inverse of the first output signal;
a third transmission gate suitable for outputting the first output signal as the sum signal in response to the carry input signal and the inverse of the carry input signal; and
a fourth transmission gate suitable for outputting the inverse of the first output signal as the sum signal in response to the carry input signal and the inverse of the carry input signal.

6. The full adder circuit of claim 1 , wherein the third logical operation unit includes:
a first pull-up unit electrically disposed between a power voltage and a first node and suitable for pull-up driving the first node in response to the inverse of the second input signal and the first output signal;
a second pull-up unit electrically disposed between the power voltage and a second node and suitable for pull-up driving the second node in response to the inverse of the first output signal and the sum signal;
a first pull-down unit electrically disposed between the first node and a ground voltage and suitable for pull-down driving the first node in response to the inverse of the first output signal and the inverse of the second input signal; and
a second pull-down unit electrically disposed between the second node and the ground voltage and suitable for pull-down driving the second node in response to the sum signal and the first output signal, and
wherein the first node and the second node are respectively disposed between the power voltage and the ground voltage.

7. The full adder circuit of claim 6 , wherein the carry output signal is the voltage level of the first node driven by the first pull-up and pull-down units.

8. The full adder circuit of claim 6 , wherein the carry output signal is the voltage level of the second node driven by the second pull-up and pull-down units.

9. The full adder circuit of claim 6 , wherein the first pull-up unit includes:
a first PMOS transistor suitable for controlling electrical connection between the power voltage and a first middle node in response to the inverse of the second input signal; and
a second PMOS transistor suitable for controlling electrical connection between the first middle node and the first node in response to the first output signal, and
wherein the first middle node is disposed between the power voltage and the first node.

10. The full adder circuit of claim 6 , wherein the second pull-up unit includes:
a third PMOS transistor suitable for controlling electrical connection between the power voltage and a second middle node in response to the inverse of the first output signal; and
a fourth PMOS transistor suitable for controlling electrical connection between the second middle node and the second node in response to the sum signal, and
wherein the second middle node is disposed between the power voltage and the second node.

11. The full adder circuit of claim 6 , wherein the first pull-down unit includes:
a first NMOS transistor suitable for controlling electrical connection between the first node and a third middle node in response to the inverse of the first output signal; and
a second NMOS transistor suitable for controlling electrical connection between the third middle node and the ground voltage response to the inverse of the second input signal, and
wherein the third middle node is disposed between the first node and the ground voltage.

12. The full adder circuit of claim 6 , wherein the second pull-down unit includes:
a third NMOS transistor suitable for controlling electrical connection between the second node and a fourth middle node in response to the sum signal; and
a fourth NMOS transistor suitable for controlling electrical connection between the fourth middle node and the ground voltage in response to the first output signal, and
wherein the fourth middle node is disposed between the second node and the ground voltage.

13. A semiconductor device, comprising:
a first logical operation unit suitable for outputting an inverse of the second input signal and a first output signal corresponding to either a second input signal or the inverse of the second input signal in response to a first input signal;
a second logical operation unit suitable for outputting an inverse of the first output signal and a sum signal corresponding to either the first output signal or an inverse of the first output signal in response to a carry input signal; and
a third logical operation unit suitable for outputting a carry output signal in response to the inverse of the second input signal, the first output signal, the inverse of the first output signal, and the sum signal.

14. The semiconductor device of claim 13 , wherein the first logical operation unit includes:
a first inverting unit suitable for inverting the first input signal to output the inverse of the first input signal;
a second inverting unit inverting the second input signal to output the inverse of the second input signal;
a first switching unit outputting the second input signal as the first output signal in response to the first input signal and the inverse of the first input signal; and
a second switching unit suitable for outputting the inverse of the second input signal as the first output signal in response to the first input signal and the inverse of the first input signal.

15. The semiconductor device of claim 13 , wherein the first logical operation unit is suitable for XOR operation for the first signal and the second input signal.

16. The semiconductor device of claim 13 , w

Assignees

• Sk Hynix Inc

Inventors

• Kim Chang-Hyun

Classifications

• G06F7/501 Primary

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• G06F7/50 Primary

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title