Buffer stage and control circuit

Patent metadata

Field	Value
Publication number	US-10613560-B2
Application number	US-201715647469-A
Country	US
Kind code	B2
Filing date	Jul 12, 2017
Priority date	Aug 5, 2016
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A buffer stage includes a control circuit. The control circuit includes a voltage generator, a voltage-to-current converter, and a current-to-voltage converter. The voltage generator is configured to generate a compensation voltage. The voltage-to-current converter is configured to convert the compensation voltage into a compensation current. The current-to-voltage converter is configured to convert the compensation current into a recovery compensation voltage. The recovery compensation voltage is arranged for modifying an output voltage of the buffer stage.

First claim

What is claimed is:

1. A buffer stage, comprising:
a control circuit, comprising:
a voltage generator, configured to generate a compensation voltage;
a voltage-to-current converter, configured to convert the compensation voltage into a compensation current; and
a current-to-voltage converter, configured to convert the compensation current into a recovery compensation voltage;
wherein the recovery compensation voltage is a sum of an input voltage of the buffer stage and a voltage produced by the current-to-voltage converter such that the recovery compensation voltage modifies an output voltage of the buffer stage; and
wherein the current-to-voltage converter comprises a first resistor including a first terminal and a second terminal, the first terminal being directly coupled to an input node of the buffer stage and the second terminal being directly coupled to a gate of a source follower.

2. The buffer stage as claimed in claim 1 , wherein the source follower is coupled to the control circuit and configured to generate the output voltage of the buffer stage.

3. The buffer stage as claimed in claim 1 , wherein the source follower comprises:
a first N-type transistor, wherein the first N-type transistor has a control terminal coupled to a first node, a first terminal coupled to an output node of the buffer stage, and a second terminal coupled to a supply voltage; and
a first current sink, drawing a first sink current from the output node of the buffer stage;
wherein the first resistor is coupled between the input node of the buffer stage and the first node.

4. The buffer stage as claimed in claim 3 , wherein the voltage generator comprises:
a first current source, supplying a first source current to a second node; and
a second N-type transistor, wherein the second N-type transistor has a control terminal coupled to the second node, a first terminal coupled to a ground voltage, and a second terminal coupled to the second node.

5. The buffer stage as claimed in claim 4 , wherein the voltage-to-current converter comprises:
an operational amplifier, wherein the operational amplifier has a positive input terminal coupled to a third node, a negative input terminal coupled to the second node, and an output terminal coupled to a fourth node;
a first P-type transistor, wherein the first P-type transistor has a control terminal coupled to the fourth node, a first terminal coupled to the supply voltage, and a second terminal coupled to the third node;
a second resistor, coupled between the third node and the ground voltage; and
a second P-type transistor, wherein the second P-type transistor has a control terminal coupled to the fourth node, a first terminal coupled to the supply voltage, and a second terminal coupled to the first node.

6. The buffer stage as claimed in claim 5 , wherein a resistance of the second resistor is substantially equal to a resistance of the first resistor.

7. The buffer stage as claimed in claim 5 , wherein the voltage-to-current converter further comprises:
a capacitor, coupled between the fourth node and the third node.

8. The buffer stage as claimed in claim 3 , wherein the voltage generator comprises:
a first current source, supplying a first source current to a second node; and
a second N-type transistor, wherein the second N-type transistor has a control terminal coupled to a third node, a first terminal coupled to a ground voltage, and a second terminal coupled to the second node.

9. The buffer stage as claimed in claim 8 , wherein the voltage-to-current converter comprises:
a third N-type transistor, wherein the third N-type transistor has a control terminal coupled to the second node, a first terminal coupled to the third node, and a second terminal coupled to a fourth node;
a second resistor, coupled between the third node and the ground voltage;
a first P-type transistor, wherein the first P-type transistor has a control terminal coupled to the fourth node, a first terminal coupled to the supply voltage, and a second terminal coupled to the fourth node; and
a second P-type transistor, wherein the second P-type transistor has a control terminal coupled to the fourth node, a first terminal coupled to the supply voltage, and a second terminal couple to the first node.

10. The buffer stage as claimed in claim 9 , wherein a resistance of the second resistor is substantially equal to a resistance of the first resistor.

11. The buffer stage as claimed in claim 1 , wherein the source follower comprises:
a first P-type transistor, wherein the first P-type transistor has a control terminal coupled to a first node, a first terminal coupled to an output node of the buffer stage, and a second terminal coupled to a ground voltage; and
a first current source, supplying a first source current to the output node of the buffer stage;
wherein the first resistor is coupled between the input node of the buffer stage and the first node.

12. The buffer stage as claimed in claim 11 , wherein the voltage generator comprises:
a first current sink, drawing a first sink current from a second node; and
a second P-type transistor, wherein the second P-type transistor has a control terminal coupled to a third node, a first terminal coupled to a supply voltage, and a second terminal coupled to the second node.

13. The buffer stage as claimed in claim 12 , wherein the voltage-to-current converter comprises:
a third P-type transistor, wherein the third P-type transistor has a control terminal coupled to the second node, a first terminal coupled to the third node, and a second terminal coupled to a fourth node;
a second resistor, coupled between the supply voltage and the third node;
a first N-type transistor, wherein the first N-type transistor has a control terminal coupled to the fourth node, a first terminal coupled to the ground voltage, and a second terminal coupled to the fourth node; and
a second N-type transistor, wherein the second N-type transistor has a control terminal coupled to the fourth node, a first terminal coupled to the ground voltage, and a second terminal coupled to the first node.

14. The buffer stage as claimed in claim 13 , wherein a resistance of the second resistor is substantially equal to a resistance of the first resistor.

15. The buffer stage as claimed in claim 1 , wherein the source follower comprises:
a first P-type transistor, wherein the first P-type transistor has a control terminal coupled to a first node, a first terminal coupled to a second node, and a second terminal coupled to a ground voltage;
a first current source, supplying a first source current to the second node;
a first N-type transistor, wherein the first N-type transistor has a control terminal coupled to the second node, a first terminal coupled to an output node of the buffer stage, and a second terminal coupled to a supply voltage; and
a first current sink, drawing a first sink current from the output node of the buffer stage;
wherein the first resistor is coupled between the input node of the buffer stage and the first node.

16. The buffer stage as claimed in claim 15 , wherein the voltage generator comprises:
a second current sink, drawing a second sink current from a third node;
a second P-type transistor, wherein the second P-type transistor has a control terminal coupled to a fourth node, a first terminal coupled to the supply voltage, and a second terminal coupled to the third node;
a second current source, supplying a second source current to a fifth node; and
a second N-type transistor, wherein the second N-type transistor has a cont

Assignees

• Mediatek Inc

Inventors

• Tsai Chihhou

Classifications

• H03F2200/21

  Bias resistors are added at the input of an amplifier · CPC title

• H03F1/301

  in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence) · CPC title

• H03F2200/555

  A voltage generating circuit being realised for biasing different circuit elements · CPC title

• G05F3/26 Primary

  Current mirrors · CPC title

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title