Substrate structure with selective surface finishes for flip chip assembly

Patent metadata

Field	Value
Publication number	US-10607960-B2
Application number	US-201916376619-A
Country	US
Kind code	B2
Filing date	Apr 5, 2019
Priority date	Aug 6, 2015
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish.

First claim

What is claimed is:

1. A method comprising:
providing a substrate body with a first metal structure and a second metal structure formed on a top surface of the substrate body, wherein the first metal structure has a first finish area and the second metal structure has a second finish area;
forming a first surface finish over at least one portion of the first finish area;
forming a second surface finish over at least one portion of the second finish area, wherein the second surface finish has a different surface activity compared to the first surface finish;
applying a flux material to the top surface of the substrate body to cover the first metal structure with the first surface finish and the second metal structure with the second surface finish; and
coupling a flip chip die to the first finish area and the second finish area, wherein:
the flip chip die includes a die body, a first interconnect structure, and a second interconnect structure; and
the first interconnect structure extends from the die body toward the first finish area, and the second interconnect structure extends from the die body toward the second finish area.

2. The method of claim 1 wherein the first surface finish comprises gold and the second surface finish does not comprise gold.

3. The method of claim 1 wherein the first surface finish is electroless nickel electroless palladium immersion gold (ENEPIG), which has a first layer formed of gold with a thickness between 0.06 μm and 0.14 μm, a second layer formed of palladium with a thickness between 0.08 μm and 0.16 μm, and a third layer formed of nickel with a thickness between 0.3 μm and 0.5 μm.

4. The method of claim 3 wherein forming the first surface finish comprises:
forming the third layer over the at least one portion of the first finish area by an electroless nickel bath;
forming the second layer over the third layer by an electroless palladium bath; and
forming the first layer over the second layer by an immersion gold bath.

5. The method of claim 1 wherein the second surface finish is an organic surface protectorant (OSP).

6. The method of claim 5 wherein the second surface finish is provided by an inline submersion process.

7. The method of claim 1 wherein the first surface finish is electroless nickel electroless palladium immersion gold (ENEPIG), bussless NiAu, or electroless palladium immersion gold (EPIG), and the second surface finish is an organic surface protectorant (OSP).

8. The method of claim 7 wherein:
the first interconnect structure includes a first solder cap and a first pillar extending outward from the die body to the first solder cap, and the second interconnect structure includes a second solder cap and a second pillar extending outward from the die body to the second solder cap; and
the first solder cap is coupled to the first finish area, and the second solder cap is coupled to the second finish area.

9. The method of claim 8 wherein coupling a flip chip die to the first finish area and the second finish area comprises:
placing the first solder cap in contact with the first surface finish on the first finish area and the second solder cap in contact with the second surface finish on the second finish area through the flux material; and
reflowing the first solder cap and the second solder cap, wherein:
the flux material and the second surface finish on the second finish area are substantially consumed; and
the first solder cap forms a first solder joint in contact with the first surface finish on the first finish area, and the second solder cap forms a second solder joint in contact with the second metal structure.

10. The method of claim 9 further comprising forming a mold compound over the substrate body to encapsulate the flip chip die.

11. The method of claim 1 wherein the second surface finish is formed over a portion of the first finish area.

12. The method of claim 1 wherein the first surface finish is formed over a portion of the second finish area.

13. A method comprising:
providing a substrate body and a first metal structure formed over a top surface of the substrate body, wherein the first metal structure has a first finish area and a second finish area, and the first finish area of the first metal structure is surrounded by the second finish area of the first metal structure;
forming a first surface finish over the first finish area of the first metal structure; and
forming a second surface finish over the second finish area of the first metal structure, wherein the second surface finish is different from the first surface finish.

14. The method of claim 13 wherein the first surface finish comprises gold and the second surface finish does not comprise gold.

15. The method of claim 13 wherein the first surface finish is electroless nickel electroless palladium immersion gold (ENEPIG), which has a first layer formed of gold with a thickness between 0.06 μm and 0.14 μm, a second layer formed of palladium with a thickness between 0.08 μm and 0.16 μm, and a third layer formed of nickel with a thickness between 0.3 μm and 0.5 μm.

16. The method of claim 15 wherein forming the first surface finish comprises:
forming the third layer over at least one portion of the first finish area by an electroless nickel bath;
forming the second layer over the third layer by an electroless palladium bath; and
forming the first layer over the second layer by an immersion gold bath.

17. The method of claim 13 wherein the second surface finish is an organic surface protectorant (OSP).

18. The method of claim 17 wherein the second surface finish is provided by an inline submersion process.

19. The method of claim 13 wherein the first surface finish is electroless nickel electroless palladium immersion gold (ENEPIG), bussless NiAu, or electroless palladium immersion gold (EPIG), and the second surface finish is an organic surface protectorant (OSP).

20. The method of claim 13 wherein the first finish area corresponds to a first portion of a pad, and the second finish area corresponds to a second portion of the pad, wherein the pad is configured to receive a wirebond or interconnect structure of a die.

21. The method of claim 13 further comprising coupling a flip chip die, which includes a die body and a first interconnect structure, to the first metal structure, wherein the first interconnect structure extends outward from the die body and is in contact with the first surface finish on the first metal structure.

Assignees

• Qorvo Us Inc

Inventors

• Morris Thomas Scott
• Hartmann Robert

Classifications

• H01L2224/16225

  Electricity · mapped topic

• H01L2224/81815

  Electricity · mapped topic

• H01L2224/1403

  Electricity · mapped topic

• H01L2224/81143

  Electricity · mapped topic

• H01L2224/81444

  Electricity · mapped topic