Semiconductor package having a substrate structure with selective surface finishes

Patent metadata

Field	Value
Publication number	US-9935066-B2
Application number	US-201615224977-A
Country	US
Kind code	B2
Filing date	Aug 1, 2016
Priority date	Aug 6, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

The present disclosure relates to a semiconductor package having a substrate structure with selective surface finishes, and a process for making the same. The disclosed semiconductor package includes a substrate body, a first metal structure having a first finish area and a second finish area, a second metal structure having a third finish area, a surface finish, and a tuning wire. The first metal structure and the second metal structure are formed over the substrate body. The surface finish is provided over the first finish area of the first metal structure and at least a portion of the third finish area of the second metal structure. The surface finish is not provided over the second finish area of the first metal structure. The tuning wire is coupled between the first finish area and at least one portion of the third finish area.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate body having a top surface;
a first finished metal structure comprising a first metal structure that is formed over the top surface of the substrate body and has a first finish area and a second finish area, wherein the first finish area is finished with a first surface finish and the second finish area is not finished with the first surface finish;
a second finished metal structure comprising a second metal structure that is formed over the top surface of the substrate body and has a third finish area, wherein at least one portion of the third finish area is finished with the first surface finish;
a third finished metal structure comprising a third metal structure that is formed over the top surface of the substrate body and has a fourth finish area, wherein at least one portion of the fourth finish area is finished with the first surface finish;
a tuning wire coupled between the first finish area and the at least one portion of the third finish area; and
a flip chip die having a die body and a first interconnect structure, wherein the first interconnect structure extends outward from the die body and is coupled to the at least one portion of the fourth finish area.

2. The apparatus of claim 1 wherein the first surface finish is electroless nickel electroless palladium immersion gold (ENEPIG).

3. The apparatus of claim 2 wherein the first surface finish comprises:
a first layer formed of gold with a thickness between 0.06 μm and 0.14 μm;
a second layer formed of palladium with a thickness between 0.08 μm and 0.16 μm; and
a third layer formed of nickel with a thickness between 0.3 μm and 0.5 μm, wherein the third layer is over the first finish area, the second layer is over the third layer, and the first layer is over the second layer.

4. The apparatus of claim 1 wherein the first surface finish is of one of a group consisting of electroless palladium immersion gold (EPIG), bussless nickel gold, and electroless nickel.

5. The apparatus of claim 1 wherein the second surface area is finished with a second surface finish that has a different surface activity compared to the first surface finish.

6. The apparatus of claim 1 wherein the first surface area corresponds to a pad and the second surface area corresponds to a conductive trace that connects the pad to another pad or via.

7. The apparatus of claim 1 wherein the first surface finish is a multilayer finish.

8. The apparatus of claim 1 wherein the first metal structure and the second metal structure are formed of copper.

9. The apparatus of claim 1 further comprising a fourth metal structure formed over the top surface of the substrate body and the flip chip die further comprising a second interconnect structure, wherein the second interconnect structure extends outward from the die body and is coupled to the fourth metal structure.

10. A method comprising:
providing a substrate body with a first metal structure, a second metal structure and a third metal structure formed on a top surface of the substrate body, wherein the first metal structure has a first finish area and a second finish area, the second metal structure has a third finish area, and the third metal structure has a fourth finish area;
forming a first surface finish over the first finish area, at least one portion of the third finish area, and at least one portion of the fourth finish area;
forming a second surface finish over the second finish area, wherein the second surface finish has different surface activity compared to the first surface finish;
applying a flux material to the top surface of the substrate body;
coupling a tuning wire between the first finish area and the at least one portion of the third finish area; and
coupling a flip chip die to the at least one portion of the fourth finish area.

11. The method of claim 10 wherein coupling the tuning wire between the first finish area and the at least one portion of the third finish area is provided by ball bonding or wedge bonding.

12. The method of claim 10 wherein the first surface finish comprises gold and the second surface finish does not comprise gold.

13. The method of claim 10 wherein the first surface finish is ENEPIG, which has a first layer formed of gold, a second layer formed of palladium, and a third layer formed of nickel.

14. The method of claim 13 wherein forming the first surface finish comprises:
forming the third layer over the first finish area and the at least one portion of the third finish area by an electroless nickel bath;
forming the second layer over the third layer by an electroless palladium bath; and
forming the first layer over the second layer by an immersion gold bath.

15. The method of claim 10 wherein the second surface finish is an organic surface protectorant (OSP).

16. The method of claim 15 wherein the second surface finish is provided by an inline submersion process.

17. The method of claim 10 wherein the flip chip die has a die body, a solder cap and a pillar extending outward from the die body to the solder cap, and wherein coupling the flip chip die to the at least one portion of the fourth finish area comprises:
placing the solder cap in contact with the first surface finish on the at least one portion of the fourth finish area; and
reflowing the solder cap, such that the solder cap forms a solder joint in contact with the first surface finish on the at least one portion of the fourth finish area.

Assignees

• Qorvo Us Inc

Inventors

• Morris Thomas Scott
• Hartmann Robert

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07234

  Using a reflow oven · CPC title