Self-aligned junction structures
US-2018204840-A1 · Jul 19, 2018 · US
Semiconductor device and method for fabricating the same
US10607897B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10607897-B2 |
| Application number | US-201916589032-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 30, 2019 |
| Priority date | Jun 12, 2018 |
| Publication date | Mar 31, 2020 |
| Grant date | Mar 31, 2020 |
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Abstract
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A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
First claim
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What is claimed is: 1. A method for fabricating semiconductor device, comprising: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure. 2. The method of claim 1 , further comprising: forming the first fin-shaped structure on the first region and a second fin-shaped structure on the second region; removing part of the first fin-shaped structure and part of the second fin-shaped structure to form the first trench and a second trench; forming the dielectric layer in the first trench and the second trench; and planarizing the dielectric layer to form the first SDB structure and a second SDB structure. 3. The method of claim 2 , further comprising forming a liner in the first trench and the second trench before forming the dielectric layer. 4. The method of claim 3 , wherein the liner and the dielectric layer comprise different materials. 5. The method of claim 3 , wherein the liner comprises silicon oxide. 6. The method of claim 2 , further comprising: forming a first gate structure on the first SDB structure and the first fin-shaped structure and a second gate structure on the second SDB structure and the second fin-shaped structure; forming a first source/drain region adjacent to the first gate structure and a second source/drain region adjacent to the second gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure and the second gate structure into a first metal gate and a second metal gate. 7. The method of claim 2 , wherein each of the first fin-shaped structure and the second fin-shaped structure is disposed extending along a first direction and the first SDB structure and the second SDB structure are disposed extending along a second direction. 8. The method of claim 7 , wherein the first direction is orthogonal to the second direction. 9. The method of claim 1 , wherein a concentration proportion of oxygen in SiOCN is between 30% to 60%. 10. The method of claim 1 , wherein a stress of the first SDB structure is between 100 MPa to −500 MPa.
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H01L21/823878Primary
Electricity · mapped topic
Electricity · mapped topic
formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title
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- What does patent US10607897B2 cover?
- A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizi…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H01L21/823878. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).