Management of core power state transition in a microprocessor

Patent metadata

Field	Value
Publication number	US-10599207-B2
Application number	US-201715835025-A
Country	US
Kind code	B2
Filing date	Dec 7, 2017
Priority date	Jul 31, 2015
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A method and apparatus for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for the inhibited processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

First claim

What is claimed is:

1. A method for adjusting a frequency of a multi-core processor, comprising:
inhibiting one or more processor cores from exiting an idle state;
determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores;
selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores;
setting the maximum frequency for the inhibited processor cores; and
uninhibiting the processor cores requesting exit from the idle state.

2. The method of claim 1 , wherein inhibiting one or more processor cores from exiting an idle state further comprises setting a status in a control register.

3. The method of claim 1 , wherein determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores further comprises inspecting a status for each processor core in a control register.

4. The method of claim 1 , further comprising, before uninhibiting the processor cores, adjusting a voltage for each of the processor cores.

5. The method of claim 4 , wherein adjusting the voltage is based at least in part on the frequency and the total number of inhibited processor cores requesting exit from the idle state plus the number of non-idle processor cores.

6. The method of claim 1 , further comprising, before uninhibiting the processor cores requesting exit from the idle state, determining that the frequency for each of the non-idle processor cores is at or below the maximum frequency.

7. The method of claim 1 , further comprising, after uninhibiting the processor cores, re-inhibiting one or more idle processor cores from exiting an idle state.

8. The method of claim 1 , wherein setting the maximum frequency further comprises setting a frequency clipping register that sets the maximum frequency for one or more cores.

9. The method of claim 1 , wherein selecting a maximum frequency for the inhibited processor cores is further based on a state of one or more of the inhibited processor cores.

10. A system, comprising:
a processor; and
a memory, wherein the memory includes a program configured to adjust a frequency of a multi-core processor, the operations comprising:
inhibiting one or more processor cores from exiting an idle state;
determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores;
selecting a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores;
setting the maximum frequency for the inhibited processor cores; and
uninhibiting the processor cores requesting exit from the idle state.

11. The system of claim 10 , wherein inhibiting one or more processor cores from exiting an idle state further comprises setting a status in a control register.

12. The system of claim 10 , wherein determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores further comprises inspecting a status for each processor core in a control register.

13. The system of claim 10 , further comprising, before uninhibiting the processor cores, adjusting a voltage for each of the processor cores.

14. The system of claim 13 , wherein adjusting the voltage is based at least in part on the frequency and the total number of inhibited processor cores requesting exit from the idle state plus the number of non-idle processor cores.

15. The system of claim 10 , further comprising, before uninhibiting the processor cores requesting exit from the idle state, determining that the frequency for each of the non-idle processor cores is at or below the maximum frequency.

16. The system of claim 10 , further comprising, after uninhibiting the processor cores, re-inhibiting one or more idle processor cores from exiting an idle state.

17. A computer program product for adjusting a frequency of a multi-core processor, the computer program product comprising:
a non-transitory computer-readable storage medium haying computer-readable program code embodied therewith, the computer-readable program code comprising:
computer-readable program code configured to inhibit one or more processor cores from exiting an idle state;
computer-readable program code configured to determine a number of processor cores requesting exit from the idle state and a number of non-idle processor cores;
computer-readable program code configured to select a maximum frequency for the inhibited processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores;
computer-readable program code configured to set the maximum frequency for the inhibited processor cores; and
computer-readable program code configured to uninhibit the processor cores requesting exit from the idle state.

18. The computer program product of claim 17 , wherein computer-readable program code configured to inhibit one or more processor cores from exiting an idle state further comprises code for setting a status in a control register.

19. The computer program product of claim 17 , further comprising computer-readable program code configured to, before uninhibiting the processor cores, adjust a voltage for each of the processor cores.

20. The computer program product of claim 17 , further comprising computer-readable program code configured to, before uninhibiting the processor cores requesting exit from the idle state, determine that the frequency for each of the non-idle processor cores is at or below the maximum frequency.

Assignees

• IBM

Inventors

• Allen-Ware Malcolm S
• Lefurgy Charles R
• Rajamani Karthick
• Rosedahl Todd J
• Silva Guillermo J
• Still Gregory S
• Zyuban Victor

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title