Providing per core voltage and frequency control

Patent metadata

Field	Value
Publication number	US-8943334-B2
Application number	US-88912110-A
Country	US
Kind code	B2
Filing date	Sep 23, 2010
Priority date	Sep 23, 2010
Publication date	Jan 27, 2015
Grant date	Jan 27, 2015

Abstract

In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a multi-core processor having a single semiconductor die including a plurality of cores, a plurality of integrated voltage regulators each associated with one of the plurality of cores and to each provide an independent voltage to at least one of the plurality of cores, and a control logic to receive a performance state change request from an operating system (OS) for dynamic update during OS operation of a voltage/frequency of one or more cores of the plurality of cores, the control logic to determine whether to update a voltage/frequency of a first core of the plurality of cores based at least in part on a workload, a thermal design power (TDP) margin and a temperature of a portion of the single semiconductor die in which the first core is located, and control provision of the voltage/frequency to the first core independently of provision of a voltage/frequency to at least a second core of the plurality of cores, wherein the control logic is to provide a control signal to each of the plurality of integrated voltage regulators to enable the corresponding integrated voltage regulator to provide an independent voltage to the corresponding core, and wherein a first voltage is to be coupled to the multi-core processor to provide a first regulated voltage to the plurality of integrated voltage regulators.

2. The processor of claim 1 , wherein the control logic includes a power control unit of an uncore portion of the processor.

3. The processor of claim 2 , wherein the OS is aware of independent control of voltage/frequency provision to the plurality of cores.

4. The processor of claim 2 , wherein the power control unit includes an activity monitor to monitor micro-architectural operation of the plurality of cores and to dynamically select at least one of the plurality of cores for provision of an updated voltage/frequency thereto based on the micro-architectural monitoring, and independent of an operating system (OS) that provides the performance state change request.

5. A method comprising:
receiving a performance state change request to dynamically adjust a voltage/frequency provided to at least one core of a processor during operation in a power control unit of the processor;
selecting the at least one core of the processor to adjust the voltage/frequency provided thereto independently of at least one other core of the processor;
sending a control signal for the adjusted voltage to an integrated voltage regulator associated with the selected core to enable the core to operate at the adjusted voltage; and
dynamically controlling an independent voltage/frequency for a first set of cores of the processor including the at least one core, and statically controlling a second set of cores of the processor including the at least one other core to receive a fixed voltage/frequency, wherein the first set of cores are associated with a first operating system and the second set of cores are associated with a second operating system.

6. The method of claim 5 , further comprising selecting the at least one core to adjust the voltage/frequency provided thereto deterministically and not opportunistically.

7. The method of claim 5 , further comprising adjusting a first plurality of cores to execute at an increased voltage/frequency independently of a second plurality of cores, so that a thermal design power (TDP) budget for the processor is maintained.

8. The method of claim 5 , further comprising receiving the performance state change request from the first operating system, wherein the first operating system is unaware of an independent voltage control ability of the processor.

9. The method of claim 5 , wherein the first operating system is to execute non-deterministic operations and the second operating system is to execute deterministic operations.

10. A system comprising:
a processor including a plurality of cores, a plurality of integrated voltage regulators each to independently provide a voltage to at least one of the plurality of cores, and a power control unit to control the plurality of integrated voltage regulators to dynamically adjust during operating system operation one or more independent voltages provided to at least some of the plurality of cores, based at least in part on a workload, a thermal design power (TDP) of the processor, and a temperature of a portion of a die of the processor in which the at least some cores are located, the processor formed on a single semiconductor die;
an external voltage coupled to the processor to provide a first voltage to the plurality of integrated voltage regulators; and
a dynamic random access memory (DRAM) coupled to the processor.

11. The system of claim 10 , wherein the power control unit includes an activity monitor to monitor micro-architectural operation of the plurality of cores and to dynamically select at least one of the plurality of cores for provision of an updated voltage/frequency thereto based on the monitoring.

12. The system of claim 10 , wherein the power control unit is to cause dynamic adjustment to a voltage/frequency provided to an uncore logic of the processor to enable a power savings, the uncore logic including the power control unit and wherein the voltage and frequency at which the uncore logic operates is not visible to the operating system, and to apply the power savings to cause dynamic adjustment to a voltage/frequency provided to at least one of the plurality of cores.

13. The system of claim 10 , wherein the power control unit includes an activity monitor to monitor micro-architectural operation of the plurality of cores and to dynamically select at least one of the plurality of cores for provision of an updated voltage/frequency thereto, and wherein at least one other core is to be provided a fixed voltage/frequency.

14. The system of claim 13 , wherein the power control unit is to predict a usage of the at least one core in a future time period based on information from the activity monitor.

15. The method of claim 9 , wherein the non-deterministic operations comprise user-level applications and the deterministic operations comprise management operations.

Assignees

• Kumar Pankaj
• Nguyen Hang
• Houghton Christopher
• Biermann David A
• Intel Corp

Inventors

• Kumar Pankaj
• Nguyen Hang
• Houghton Christopher
• Biermann David A

Classifications

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G05F1/46

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title