Semiconductor memory device and detection clock pattern generating method thereof

Patent metadata

Field	Value
Publication number	US-10593387-B2
Application number	US-201916274860-A
Country	US
Kind code	B2
Filing date	Feb 13, 2019
Priority date	Sep 21, 2012
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

First claim

What is claimed is:

1. A method of operating a graphic memory system including a graphic processor unit (GPU) and a dynamic random access memory (DRAM) device coupled to the GPU, the DRAM including at least one error detection code pin, the method comprising:
setting a mode setting control signal of the DRAM into one of a first level or a second level;
receiving a read command from the GPU by the DRAM; outputting read data through a data pin in response to the read command by the DRAM and transmitting the read data to the GPU;
outputting cyclic redundancy check data during a first time period through a first error detection code pin by the DRAM and transmitting the cyclic redundancy check data to the GPU; and
outputting a first error detection code pattern during a second time period through the first error detection code pin by the DRAM and transmitting the first error detection code pattern to the GPU, and the second time period is different from the first time period,
wherein the first error detection code pattern is a hold pattern when the mode setting control signal is set into the first level and is a random pattern when the mode setting control signal is set into the second level respectively, and the second level is different from the first level.

2. The method of claim 1 , wherein the GPU performs a clock-data recovery (CDR) function based on the first error detection code pattern.

3. The method of claim 1 , further outputting a second error detection code pattern during the second time period through a second error detection code pin.

4. The method of claim 3 , wherein the second error detection code pattern is identical in phase with the first error detection code pattern.

5. The method of claim 3 , wherein the second error detection code pattern is inverted pattern of the first error detection code pattern, and thereby combined together with the first error detection code pattern, forms a differential signal pattern.

6. The method of claim 1 , wherein the random pattern is a pseudo random pattern generated by a pseudo random pattern generator which includes linear feedback shift registers.

7. The method of claim 1 , wherein the read data are output after CAS latency from the read command.

8. The method of claim 7 , wherein the cyclic redundancy check data are output later than the read data.

9. The method of claim 8 , wherein the cyclic redundancy check data are generated based on the read data.

10. The method of claim 1 , wherein the mode setting control signal is set during a mode register setting period.

11. A method of operating a dynamic random access memory (DRAM) device including at least one error detection code pin, the method comprising:
setting a mode setting control signal into one of a first level or a second level; receiving a read command from an external device;
outputting read data in response to the read command through a data pin;
outputting a cyclic redundancy check data through a first error detection code pin during a first time period; and
outputting a first error detection code pattern through the first error detection code pin during a second time period which is different from the first time period,
wherein the first error detection code pattern is a random pattern when the mode setting control signal is set into the first level and is a hold pattern when the mode setting control signal is set into the second level respectively, and the second level is different from the first level.

12. The method of claim 11 , wherein the first error detection code pattern is provided to the external device for a clock-data recovery function.

13. The method of claim 11 , further outputting a second error detection code pattern during the second time period through a second error detection code pin.

14. The method of claim 13 , wherein the second error detection code pattern is identical in phase with the first error detection code pattern.

15. The method of claim 13 , wherein the second error detection code pattern is inverted pattern of the first error detection code pattern, and thereby combined together with the first error detection code pattern, forms a differential signal pattern.

16. The method of claim 11 , wherein the random pattern is a pseudo random pattern generated by a pseudo random pattern generator which includes linear feedback shift registers.

17. The method of claim 11 , wherein the read data are output after CAS latency from the read command.

18. The method of claim 17 , wherein the cyclic redundancy check data are output later than the read data.

19. The method of claim 18 , wherein the cyclic redundancy check data are generated based on the read data.

20. A method of operating a dynamic random access memory (DRAM) device including at least one error detection code pin, the method comprising: setting a mode setting control signal into one of a first level or a second level; receiving a read command from an external device; outputting read data in response to the read command through a data pin; outputting a cyclic redundancy check data through a first error detection code pin during a first time period, wherein the cyclic redundancy check data are output later than the read data; and outputting a first error detection code pattern through the first error detection code pin during a second time period which is different from the first time period, wherein the first error detection code pattern is a random pattern when the mode setting control signal is set into the first level and is a hold pattern when the mode setting control signal is set into the second level respectively, and the second level is different from the first level.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Doo Su Yeon
• Bae Seungjun
• Kim Sihong
• Song Hosung

Classifications

• G11C8/18 Primary

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title