Memory subsystem in CNN based digital IC for artificial intelligence

Patent metadata

Field	Value
Publication number	US-10592804-B2
Application number	US-201916403679-A
Country	US
Kind code	B2
Filing date	May 6, 2019
Priority date	Apr 3, 2017
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem having first and second memories. The first memory includes an array of magnetic random access memory (RAM) cells for storing weights (e.g., filter coefficients) and the second memory contains SRAM for storing input signals (e.g., imagery data). The first memory may store one-time-programming weights. The memory subsystem may contain a third memory that contains magnetic RAM cells for storing one-time-programming data for security purpose. The magnetic RAM includes STT-RAM or OST-MRAM in SLC or MLC technology.

First claim

What is claimed is:

1. A digital integrated circuit for artificial intelligence comprising:
a semi-conductor substrate embedded in a single semi-conductor chip, the semi-conductor substrate containing a plurality of cellular neural networks (CNN) processing units, each CNN processing unit comprising:
CNN logic circuits; and
an embedded memory subsystem operatively coupling to the CNN logic circuits;
the embedded memory subsystem further comprising:
a first memory containing an array of magnetic random access memory cells configured for storing a set of weights; and
a second memory containing an array of static random access memory cells configured for storing the input signals that require higher endurance of balanced data read and write operations than the first memory.

2. The digital integrated circuit of claim 1 , wherein each of the magnetic random access memory cells comprises a single-level cell spin transfer torque magnetic random access memory (SLC STT-RAM) cell.

3. The digital integrated circuit of claim 1 , wherein each of the magnetic random access memory cells comprises a multi-level cell spin transfer torque magnetic random access memory (MLC STT-RAM) cell.

4. The digital integrated circuit of claim 1 , wherein said each of the magnetic random access memory cells comprises a single-level cell orthogonal spin transfer magnetic random access memory (SLC OST-MRAM) cell.

5. The digital integrated circuit of claim 1 , wherein said each of the magnetic random access memory cells comprises a multi-level cell orthogonal spin transfer magnetic random access memory (MLC OST-MRAM) cell.

6. The digital integrated circuit of claim 1 , wherein the semi-conductor substrate comprises a silicon substrate.

7. A digital integrated circuit for artificial intelligence comprising:
a semi-conductor substrate embedded in a single semi-conductor chip, containing a plurality of cellular neural networks (CNN) processing units, each CNN processing unit comprising:
CNN logic circuits; and
an embedded memory subsystem operatively coupling to the CNN logic circuits;
the embedded memory subsystem further comprising:
a first memory containing an array of magnetic random access memory cells configured for storing a set of one-time-programming weights; and
a second memory containing an array of static random access memory cells configured for storing the input signals that require higher endurance of balanced data read and write operations than the first memory.

8. The digital integrated circuit of claim 7 , wherein each of the magnetic random access memory cells comprises a single-level cell spin transfer torque magnetic random access memory (SLC STT-RAM) cell.

9. The digital integrated circuit of claim 7 , wherein each of the magnetic random access memory cells comprises a multi-level cell spin transfer torque magnetic random access memory (MLC STT-RAM) cell.

10. The digital integrated circuit of claim 7 , wherein said each of the magnetic random access memory cells comprises a single-level cell orthogonal spin transfer magnetic random access memory (SLC OST-MRAM) cell.

11. The digital integrated circuit of claim 7 , wherein said each of the magnetic random access memory cells comprises a multi-level cell orthogonal spin transfer magnetic random access memory (MLC OST-MRAM) cell.

12. The digital integrated circuit of claim 7 , wherein each of the magnetic random access memory cells has at least one MTJ element and each MTJ element contains an oxide barrier layer.

Assignees

• Gyrfalcon Tech Inc

Inventors

• Torng Chyu-Jiuh
• Yang Lin
• Dong Qi

Classifications

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/5607

  using magnetic storage elements · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title