Biased amplifier

Patent metadata

Field	Value
Publication number	US-10587235-B2
Application number	US-201815912477-A
Country	US
Kind code	B2
Filing date	Mar 5, 2018
Priority date	Oct 16, 2017
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

First claim

What is claimed is:

1. An amplifier, comprising:
a bias circuit configured to generate a bias voltage with respect to ground; and
an open-loop gain stage comprising:
a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a gate terminal coupled to a first node, a source terminal coupled to a second node, a drain terminal coupled to a third node, and a bulk connection coupled to the bias circuit;
a second PMOS having a gate terminal coupled to a ground node, a source terminal coupled to the second node, a drain terminal coupled to a fourth node, and a bulk connection coupled to the bias circuit;
a first n-type MOSFET (NMOS) having a drain terminal and a gate terminal coupled to the third node and a source terminal coupled to a fifth node;
a second NMOS having a drain terminal coupled to the fourth node, a gate terminal coupled to the third node; and a source terminal coupled to the fifth node, wherein the gain stage is configured to couple to an adjustable resistor positioned between the third node and the fourth node; and
a buffer stage coupled to the open-loop gain stage at the fourth node and comprising a super source follower.

2. The amplifier of claim 1 , further comprising a first diode and a second diode coupled in opposing polarities between the first node and the ground node, wherein the first node is an input of the amplifier.

3. The amplifier of claim 1 , wherein the bias circuit comprises a third NMOS having a drain terminal and a gate terminal coupled to the buffer stage and a source terminal configured to couple to the fifth node via a first resistor, wherein the bias circuit is further configured to couple to a second resistor and a first capacitor, each positioned between a sixth node and the fifth node, and wherein the sixth node is coupled to the bulk connection of the first PMOS and the second PMOS.

4. The amplifier of claim 1 , wherein the buffer stage comprises:
a third PMOS having a gate terminal coupled to the fourth node, a source terminal coupled to a seventh node, and a drain terminal coupled to an eighth node;
a fourth NMOS having a gate terminal coupled to the bias circuit, a source terminal configured to couple to the fifth node via a third resistor, and a drain terminal coupled to the eighth node; and
a fifth NMOS having a gate terminal coupled to the eighth node, a drain terminal coupled to the seventh node, and a source terminal coupled to the fifth node, wherein the buffer stage is configured to couple to a second capacitor and a fourth resistor coupled in series between the eighth node and the fifth node, and wherein the seventh node is an output of the amplifier.

5. The amplifier of claim 1 , wherein the open-loop gain stage is further configured to couple to a fifth resistor between the source terminal of the first PMOS and the second node and a sixth resistor between the source terminal of the second PMOS and the second node.

6. An integrated circuit comprising:
an input node;
an output node;
a gain stage coupled to the input node, wherein the gain stage includes:
a first transistor that includes a gate coupled to the input node, a source coupled to a second node, and a drain coupled to a third node;
a second transistor that includes a gate coupled to a ground node, a source coupled to the second node, and a drain coupled to a fourth node;
a third transistor that includes a gate coupled to the third node, a drain coupled to the third node, and a source coupled to the ground node; and
a fourth transistor that includes a gate coupled to the third node, a drain coupled to the fourth node, and a source coupled to the ground node;

a bias circuit coupled to a bulk connection of the first transistor and to a bulk connection of the second transistor; and
a buffer stage coupled to the fourth node of the gain stage, wherein the buffer stage includes:
a fifth transistor that includes a gate coupled to the fourth node, a source coupled to the output node, and a drain coupled to a seventh node; and
a sixth transistor that includes a gate coupled to the bias circuit, a source coupled to the ground node, and a drain coupled to the seventh node.

7. The integrated circuit of claim 6 , wherein the bias circuit includes a fifth node coupled to the gate of the sixth transistor of the buffer stage and a sixth node coupled to the bulk connection of the first transistor and to the bulk connection of the second transistor.

8. The integrated circuit of claim 7 , wherein the bias circuit includes a fifth transistor that includes a gate coupled to the fifth node, a source coupled to the ground node by a first resistor, and a drain coupled to the fifth node.

9. The integrated circuit of claim 8 , wherein the bias circuit further includes a second resistor and capacitor coupled in parallel between the ground node and the sixth node.

10. The integrated circuit of claim 6 , wherein the buffer stage further includes:
a seventh transistor that includes a gate coupled to the seventh node, a source coupled to the ground node, and a drain coupled to the output node.

11. The integrated circuit of claim 10 , wherein the buffer stage further includes a capacitor and a resistor coupled in series between the seventh node and the ground node.

12. The integrated circuit of claim 6 , wherein the gain stage further includes a first diode and a second diode coupled in opposing polarities between the input node and the ground node.

13. The integrated circuit of claim 6 , wherein the buffer stage is a source follower buffer stage.

14. The integrated circuit of claim 6 , wherein the gain stage further includes an impedance element coupled between the third node and the fourth node.

15. The integrated circuit of claim 14 , wherein the impedance element coupled between the third node and the fourth node is a variable impedance element.

16. An integrated circuit comprising:
a capacitive sensor; and
an amplifier circuit coupled to the capacitive sensor, wherein the amplifier circuit includes:
a gain stage that includes:
a first p-type transistor having a gate terminal coupled to an input node to which the capacitive sensor is coupled, a source terminal coupled to a second node by a first resistor, and a drain terminal coupled to a third node;
a second p-type transistor having a gate terminal coupled to a ground node, a source terminal coupled to the second node by a second resistor, and a drain terminal coupled to a fourth node;
a first n-type transistor having a gate terminal coupled to the third node, a source terminal coupled to the ground node, and a drain terminal coupled to the third node;
a second n-type transistor having a gate terminal coupled to the third node, a source terminal coupled to the ground node, and a drain terminal coupled to the fourth node; and
an impedance element coupled between the third node and the fourth node;

a buffer stage coupled to the fourth node; and
a bias circuit coupled to a bulk of the first p-type transistor and to a bulk of the second p-type transistor.

17. The integrated circuit of claim 16 , wherein the amplifier circuit further includes an output node and wherein the buffer stage includes:
a third p-type transistor that includes a gate terminal coupled to the fourth node, a source terminal coupled to the output node, and a drain terminal coupled to a fifth node; and
a third n-type transistor that includes a gate terminal coupled to the buffer stage, a source terminal coupled to the ground node, and a drain terminal coupled to the fifth node.

18. The

Assignees

• Texas Instruments Inc

Inventors

• Prasad Sudheer

Classifications

• H03F2203/45392

  the AAC comprising resistors in the source circuit of the AAC before the common source coupling · CPC title

• H03F3/45461

  Complementary cross coupled types · CPC title

• H03F2200/12

  A bias circuit for some stages being shown using transmission lines · CPC title

• H03F2203/45354

  the AAC comprising offset means · CPC title

• H03F3/45502 Primary

  Controlling the common emitter circuit of the differential amplifier · CPC title