Biased amplifier

Patent metadata

Field	Value
Publication number	US-11025216-B2
Application number	US-202016804253-A
Country	US
Kind code	B2
Filing date	Feb 28, 2020
Priority date	Oct 16, 2017
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

First claim

What is claimed is:

1. An amplifier, comprising:
a bias circuit; and
a buffer stage coupled to the bias circuit and comprising:
a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a source terminal coupled to a second node; a gate terminal coupled to a third node, a drain terminal coupled to a fourth node, and a bulk connection coupled to a first node, a first resistor coupleable between the first node and the second node;
a first n-type MOSFET (NMOS) having a drain terminal coupled to the fourth node, a gate terminal coupled to the bias circuit, and a source terminal configured to couple to a fifth node via a second resistor; and
a second NMOS having a drain terminal coupled to the second node, a gate terminal coupled to the fourth node, and a source terminal coupled to the fifth node, wherein the buffer stage is configured to couple to a first capacitor and a third resistor coupled in series between the fourth node and the fifth node, and wherein the second node is an output of the amplifier.

2. The amplifier of claim 1 , wherein the bias circuit comprises:
a third NMOS having a drain terminal, a gate terminal coupled to a sixth node, and a source terminal coupled to a seventh node;
a bi-polar junction transistor (BJT) having a collector terminal and a base terminal coupled to the seventh node and an emitter terminal coupled to the fifth node; and
a fourth NMOS having a drain terminal and a gate terminal coupled to the sixth node and a source terminal configured to couple to the fifth node via a fourth resistor.

3. The amplifier of claim 1 , further comprising a first diode and a second diode coupled in opposing polarities between the third node and a ground node, wherein the third node is an input of the amplifier.

4. The amplifier of claim 1 further comprising:
a third PMOS having a source terminal coupled to a voltage supply node, a gate terminal, and a drain terminal; and
a fourth PMOS having a source terminal coupled to the drain terminal of the third PMOS, a gate terminal, and a drain terminal configured to couple to the first resistor.

5. The amplifier of claim 4 further comprising a filter that includes:
a capacitor coupled between the voltage supply node and the gate terminal of the third PMOS; and
a fourth resistor coupled to the gate terminal of the third PMOS.

6. A circuit comprising:
an input node configured to couple to a sensor;
an output node;
a ground node;
a voltage supply node;
a bias circuit configured to generate a bias voltage;
a buffer stage that includes:
a first transistor that includes a gate coupled to the input node;
a first resistor coupled to the first transistor;
a second transistor coupled to the first transistor that includes a gate coupled to receive the bias voltage;
a second resistor coupled between the second transistor and the ground node; and
a third transistor coupled to the output node that includes a gate coupled to the first transistor and the second transistor.

7. The circuit of claim 6 , wherein:
the first transistor is a p-type transistor and further includes a source coupled to the first resistor and a drain coupled to a first node;
the second transistor is an n-type transistor and further includes a source coupled to the second resistor and a drain coupled to the first node; and
the gate of the third transistor is coupled to the first node.

8. The circuit of claim 7 further comprising a capacitor and a third resistor coupled in series between the first node and the ground node.

9. The circuit of claim 7 , wherein the third transistor is an n-type transistor and further includes a source coupled to the ground node and a drain coupled to the output node.

10. The circuit of claim 6 , wherein the first transistor is a p-type transistor and further includes a source and a bulk coupled such that the first resistor is coupled between the source of the first transistor and the bulk of the first transistor.

11. The circuit of claim 6 further comprising:
a fourth transistor and a fifth transistor coupled in series between the voltage supply node and the first resistor, wherein the fourth transistor and the fifth transistor each include a gate; and
a capacitor coupled between the voltage supply node and the gate of the fourth transistor.

12. The circuit of claim 11 , wherein:
the gate of the fifth transistor is coupled to the bias circuit to receive the bias voltage; and
the circuit further comprises at least one resistor coupled between the gate of the fifth transistor and the gate of the fourth transistor.

13. The circuit of claim 12 further comprising:
a sixth transistor and a seventh transistor coupled in series between the voltage supply node and a third resistor of the at least one resistor, wherein:
the sixth transistor and the seventh transistor each include a gate;
the at least one resistor includes a fourth resistor coupled between the gate of the fourth transistor and the gate of the sixth transistor; and
the gate of the seventh transistor is coupled to the gate of the fifth transistor.

14. The circuit of claim 6 , wherein the bias circuit includes:
a first node to provide the bias voltage;
a fourth transistor that includes a gate coupled to the first node, a drain coupled to the first node, and a source;
a third resistor coupled between the source of the fourth transistor and the ground node;
a fifth transistor that includes a gate coupled to the first node, a drain, and a source; and
a sixth transistor that includes a base coupled to the source of the fifth transistor, a collector coupled to the source of the fifth transistor, and an emitter coupled to the ground node.

15. The circuit of claim 14 further comprising:
a fourth resistor coupled to the first node;
a seventh transistor and an eighth transistor coupled in series between the voltage supply node and the fourth resistor; and
a ninth transistor and a tenth transistor coupled in series between the voltage supply node and the drain of the fifth transistor.

16. The circuit of claim 15 , wherein:
each of the seventh, eighth, ninth, and tenth transistors includes a gate;
the gate of the seventh transistor is coupled to the gate of the ninth transistor;
the gate of the eighth transistor is coupled to the gate of the tenth transistor; and
the fourth resistor is coupled between the gate of the seventh transistor and the gate of the eighth transistor.

17. A circuit comprising an input node configured to couple to a sensor;
an output node;
a first transistor that includes a gate coupled to the input node, a source coupled to the output node, a drain coupled to a first node, and a bulk;
a first resistor coupled between the source of the first transistor and the bulk of the first transistor;
a second transistor that includes a drain coupled to the first node, a gate, and a source;
a second resistor coupled between the source of the second transistor and a ground node; and
a third transistor that includes a gate coupled to the first node, a drain coupled to the output node, and a source coupled to the ground node.

18. The circuit of claim 17 further comprising a capacitor and a third resistor coupled in series between the first node and the ground node.

19. The circuit of claim 17 further comprising a bias circuit configured to provide a bias voltage, wherein the gate of the second transistor is coupled to the bias circuit to receive the bias voltage.

20. The circuit of claim 19 , wherein

Assignees

• Texas Instruments Inc

Inventors

• Prasad Sudheer

Classifications

• H03F3/45085 Primary

  Long tailed pairs (H03F3/45112, H03F3/45139 take precedence) · CPC title

• H03F2203/45342

  the AAC comprising control means on a back gate of the AAC · CPC title

• H03F2200/12

  A bias circuit for some stages being shown using transmission lines · CPC title

• H03F3/45264

  Complementary cross coupled types · CPC title

• H03F3/45461

  Complementary cross coupled types · CPC title