Electronic device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10586917-B2
Application number	US-201816203114-A
Country	US
Kind code	B2
Filing date	Nov 28, 2018
Priority date	Jan 28, 2016
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.

First claim

What is claimed is:

1. An electronic device comprising:
a semiconductor memory,
wherein the semiconductor memory comprises:
a free layer having a changeable magnetization direction;
a pinned layer having a magnetization direction pinned in a first direction;
a tunnel barrier layer interposed between the free layer and the pinned layer;
a magnetic correction layer having a magnetization direction pinned in a second direction, wherein the second direction is the opposite direction to the first direction; and
a spacer layer interposed between the pinned layer and the magnetic correction layer,

wherein the pinned layer and the magnetic correction layer exchange coupling with each other through the spacer layer, and wherein a roughness at an interface between the magnetic correction layer and the spacer layer is lower than a roughness at an interface between the spacer layer and the pinned layer.

2. The electronic device of claim 1 , wherein a first mixing layer is formed at the interface between the magnetic correction layer and the spacer layer,
wherein a second mixing layer is formed at the interface between the spacer layer and the pinned layer, and
wherein a thickness of the first mixing layer is smaller than a thickness of the second mixing layer.

3. The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory is part of the memory unit in the microprocessor.

4. The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory is part of the cache memory unit in the processor.

5. The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

6. The electronic device according to claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,
wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

7. The electronic device according to claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply;
a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;
a buffer memory configured to buffer data exchanged between the memory and the outside; and
an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,
wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

8. The electronic device of claim 1 , wherein the magnetic correction layer comprises a plurality of first layers and a plurality of second layers which are alternately stacked,
wherein each of the plurality of first layers includes a magnetic material, and
wherein each of the plurality of second layers includes a non-magnetic material.

9. The electronic device of claim 8 , wherein the magnetic material includes Co, Fe, Ni, or a combination thereof.

10. The electronic device of claim 8 , wherein the non-magnetic material includes Pt, Pd, or a combination thereof.

11. A method for fabricating an electronic device, comprising:
forming a variable resistance element at a first temperature; and
forming a magnetic correction layer over the pinned layer at a second temperature,
wherein the second temperature is lower than the first temperature,
wherein the variable resistance element includes a free layer provided over a substrate, a pinned layer provided over the free layer, a tunnel barrier layer interposed between the free layer and the pinned layer,
wherein the magnetic correction layer has a magnetization direction which is anti-parallel to the pinned layer,
wherein the first temperature is at 273K or more.

12. The method of claim 11 ,
wherein the second temperature is at 0K-75K, inclusive.

13. The method of claim 11 , wherein the forming of the magnetic correction layer comprises:
(a) cooling the substrate to the second temperature;
(b) forming a first layer over the cooled substrate;
(c) forming a second layer over the first layer;
(d) repeating the forming of the first layer and the forming of the second layer M number of times; and
(e) recooling the substrate to a third temperature,
wherein the third temperature is 0K-75K, inclusive, and
where M is a positive integer.

14. The method of claim 13 , wherein the steps (b)-(e) are repeated N number of times, and
where N is a positive integer.

15. The method of claim 14 ,
wherein N is 4-100.

16. The method of claim 13 ,
wherein M is 1-100.

Assignees

• Sk Hynix Inc
• Toshiba Memory Corp

Inventors

• Lim Jong-Koo
• Choi Won-Joon
• Kim Guk-Cheon
• Kim Yang-Kon
• Jung Ku-Youl
• Nagase Toshihiko
• Eeh Youngmin
• Watanabe Daisuke
• Sawada Kazuya
• Nagamine Makoto

Classifications

• H01L43/10

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L43/08 Primary

  Electricity · mapped topic

• H10N50/85

  Materials of the active region · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title