Zero leakage, high noise margin coupled giant spin hall based retention latch

Patent metadata

Field	Value
Publication number	US-2017200499-A1
Application number	US-201615265825-A
Country	US
Kind code	A1
Filing date	Sep 14, 2016
Priority date	Jan 8, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.

First claim

What is claimed is:

1 . A non-volatile data retention circuit configured to store complementary volatile charge states of an external latch, the non-volatile data retention circuit comprising:
a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage; a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal; and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.

2 . The non-volatile data retention circuit of claim 1 , wherein the charge current from the external latch corresponds to the complementary volatile charge states of the external latch.

3 . The non-volatile data retention circuit of claim 1 , wherein the coupled giant spin hall latch comprises:
a giant spin hall metal coupled to the write switch and the read switch and configured to pass through the charge current of the external latch; a first spin transfer torque (STT) stack at a first side of the giant spin hall metal; and a second STT stack at a second side of the giant spin hall metal opposite to the first side, wherein the first and second STT stacks extend along a direction orthogonal to an extension direction of the giant spin hall metal, and are configured to generate and store the complementary non-volatile spin states.

4 . The non-volatile data retention circuit of claim 3 , wherein the write switch comprises a first write switch and a second write switch coupled to opposite ends of the giant spin hall metal and to first and second outputs of the external latch.

5 . The non-volatile data retention circuit of claim 3 , wherein the giant spin hall metal comprises beta tantalum, platinum, and/or copper bismuth.

6 . The non-volatile data retention circuit of claim 3 , wherein, in response to the charge current flowing through the giant spin hall metal, the first STT stack is configured to exhibit magnetic moments having a parallel configuration, and the second STT stack is configured to exhibit magnetic moments having an anti-parallel configuration, and
wherein the first and second STT stacks are configured to maintain their parallel and anti-parallel configurations even when no power is provided to the non-volatile data retention circuit.

7 . The non-volatile data retention circuit of claim 6 , wherein the parallel configuration of the first STT stack and the anti-parallel configuration of the second STT stack correspond to storage of the complementary non-volatile spin states at the first and second STT stacks.

8 . The non-volatile data retention circuit of claim 3 , wherein each of the first and second STT stacks comprise:
a free layer comprising magnetic material and configured to respond to a spin current corresponding to the charge current flowing through the giant spin hall metal based on a giant spin hall effect, and to exhibit a free magnetic moment substantially orthogonal in direction to the generated spin current; a fixed layer comprising magnetic material and exhibiting a fixed magnetic moment unaffected by stray fields resulting from the charge current flowing through the giant spin hall metal; and a non-magnetic layer between the free and fixed layers and configured to magnetically isolate the free magnetic moment of the free layer from the fixed magnetic moment of the fixed layer and to maintain any existing difference in directionality of the free and fixed magnetic moments.

9 . The non-volatile data retention circuit of claim 8 , wherein the free magnetic moment of the first STT stack is parallel with that of the fixed magnetic moment of the second STT stack.

10 . The non-volatile data retention circuit of claim 8 , wherein, in response to the charge current flowing through the giant spin hall metal, the free layer of the first STT stack is configured to exhibit a first free magnetic moment parallel with the fixed magnetic moment of the corresponding fixed layer, and the free layer of the second STT stack is configured to exhibit a second free magnetic moment anti-parallel with the fixed magnetic moment of the corresponding fixed layer.

11 . The non-volatile data retention circuit of claim 8 , wherein the non-magnetic layer comprises one or more of crystalline MgO and amorphous aluminum oxide, and
wherein each of the free layers of the first and second STT stacks comprise one or more of CoFeB, Fe, and CoFe.

12 . The non-volatile data retention circuit of claim 8 , wherein each of the fixed layers of the first and second STT stacks comprise a synthetic antiferromagnetic layer.

13 . The non-volatile data retention circuit of claim 12 , wherein the synthetic antiferromagnetic layer comprises a plurality of magnetic layers antiferromagnetically coupled through and interleaved with thin conductive layers.

14 . The non-volatile data retention circuit of claim 1 , wherein coupled giant spin hall latch is configured to continue storing the complementary non-volatile spin states even when no power is provided to the non-volatile data retention circuit.

15 . A data retention system comprising:
a first volatile data latch configured to store complementary volatile charge states; a status indicator configured to generate a sleep signal and a wake signal based on a power mode of the data retention system; a non-volatile data retention circuit comprising:
a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the first volatile data latch in response to receiving a charge current from the first volatile data latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage;
a write switch configured to selectively enable flow of the charge current from the first volatile data latch to the coupled giant spin hall latch in response to the sleep signal; and
a read switch configured to selectively enable the application of the read voltage to the coupled giant spin hall latch in response to the wake signal; and
a second output volatile data latch configured to read the complementary non-volatile spin states from the non-volatile data retention circuit at power on.

16 . The data retention system of claim 15 , wherein the first volatile data latch is configured to store volatile complementary states only when powered on, and
wherein the first and second volatile data latches are the same.

17 . A method of retaining complementary volatile charge states of a volatile data latch when powered down, the method comprising:
receiving a sleep signal indicative of initiation of power down mode from a status indicator; and in response to receiving the sleep signal:
coupling, via a write switch, output nodes of the volatile data latch to opposite ends of a giant spin hall metal of a coupled giant spin hall latch to receive a charge current from the volatile data latch through the giant spin hall metal; and
generating and storing, by the coupled giant spin ha

Assignees

• Samsung Electronics Co Ltd

Inventors

• Rakshit Titash
• Obradovic Borna

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• H01L43/04

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• G11C14/0081 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• H01L43/10

  Electricity · mapped topic