3D-microstrip branchline coupler

Patent metadata

Field	Value
Publication number	US-10586752-B2
Application number	US-201815997837-A
Country	US
Kind code	B2
Filing date	Jun 5, 2018
Priority date	Oct 16, 2015
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.

First claim

What is claimed:

1. A method of manufacturing a semiconductor structure, comprising:
forming a first through silicon via which forms a first port of a three dimensional (3D) branchline coupler;
forming a second through silicon via which forms a second port of the 3D branchline coupler;
forming a third through silicon via which forms a third port of the 3D branchline coupler; and
forming a fourth through silicon via which forms a fourth port of the 3D branchline coupler,
wherein the first, second, third, and fourth through silicon vias are formed in a wafer.

2. The method of claim 1 , wherein the first port is an input signal port.

3. The method of claim 2 , wherein the input signal port is split into two quadrature signals at the second port and the third port.

4. The method of claim 3 , wherein the two quadrature signals at the second port and the third port are of equal amplitude and with 90 phase difference.

5. The method of claim 1 , wherein the wafer is a semiconductor wafer.

6. The method of claim 1 , wherein the wafer is a silicon wafer.

7. The method of claim 1 , further comprising thinning the wafer prior to forming the first, second, third, and fourth through silicon vias.

8. The method of claim 1 , further comprising forming insulator layers on a top side and a bottom side of the wafer.

9. The method of claim 8 , wherein the insulator layers cover conductive lines that connects ones of the first, second, third, and fourth through silicon vias.

10. The method of claim 1 , further comprising forming a ground shield structure surrounding the 3D branchline coupler, wherein the ground shield structure comprises through silicon vias.

11. A method of manufacturing a semiconductor structure, comprising:
thinning a wafer;
forming a coupler comprising: plural through silicon vias in the wafer; and plural conductive lines connecting ones of the plural through silicon vias; and
forming a ground shield structure surrounding the coupler.

12. The method of claim 11 , wherein the ground shield structure comprises other through silicon vias and other conductive lines.

13. The method of claim 11 , further comprising forming insulator layers on the plural conductive lines on upper and lower surfaces of the wafer.

14. The method of claim 11 , wherein the wafer is a semiconductor wafer.

15. The method of claim 11 , wherein the wafer is a silicon wafer.

Assignees

• IBM

Inventors

• Dewitt Barbara S
• Mina Essam
• Rahman B M Farid
• Wang Guoan

Classifications

• H01P3/003 Primary

  Coplanar lines · CPC title

• H01P11/001

  Manufacturing waveguides or transmission lines of the waveguide type · CPC title

• H01P3/081

  Microstriplines · CPC title

• H01P3/026

  Coplanar striplines [CPS] · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title