Digital filtering for analog gain/phase errors

Patent metadata

Field	Value
Publication number	US-10581406-B2
Application number	US-201816005673-A
Country	US
Kind code	B2
Filing date	Jun 11, 2018
Priority date	Jun 9, 2017
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

First claim

The invention claimed is:

1. A circuit for use in a system for radio frequency (RF) communication including a transmit (TX) end, and a receive (RX) end to receive an RF RX signal at an RF frequency within a target frequency band, the circuit comprising:
an input port to receive the RF RX signal;
an analog-to-digital converter (ADC) with an input coupled through an analog signal path to the input port, and with an output coupled through a digital signal path to an output port;
a digital step attenuator (DSA) coupled to the analog signal path, and configured to attenuate the RF RX signal with selectable DSA attenuation steps based on a DSA control signal, and generate a DSA output that includes, for at least some of the DSA attenuation steps, DSA phase errors and/or DSA gain errors;
the ADC configured to convert an input signal corresponding to the DSA output to a digital ADC output provided to the digital signal path;
downconverter circuitry included in at least one of the analog signal path and the digital signal path, and configured to downconvert a signal at the RF frequency to a signal at a baseband frequency;
a DSA frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with a complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

2. The circuit of claim 1 , wherein:
the parameterized filter has a filter response in the frequency domain that is linear across frequency; and
the complex filter parameter having a real part determining a slope of the linear phase change response of the parameterized filter over a pre-defined frequency range within the target frequency band to correct the frequency-dependent DSA phase error, and/or an imaginary part determining a slope of the linear gain change response of the parameterized filter over a pre-defined frequency range within the target frequency band to correct the frequency-dependent DSA gain error.

3. The circuit of claim 1 , wherein the ADC is an RF ADC that converts the DSA output at the RF frequency to a digital RF signal.

4. The circuit of claim 1 , further comprising
a digital downconverter (DDC) in the digital signal path to downconvert the digital ADC output to the baseband frequency;
the DDC including a decimation filter with at least a final decimation stage;
the DSA frequency-dependent corrector filter included in the digital signal path in front of the final decimation stage.

5. The circuit of claim 1 , wherein, for each DSA attenuation step, for a parameterized filter:
the complex filter parameter is determined in a calibration operation based on responses of the DSA to two tone signals in the target frequency band.

6. The circuit of claim 5 , wherein the two tone signals are near the band edges for the target frequency band.

7. The circuit of claim 1 , further comprising:
DSA frequency-independent corrector circuitry included in the digital signal path, and for each DSA attenuation step, configured, based on the DSA control signal, to correct frequency-independent DSA errors in phase and gain that are independent of frequency, the DSA frequency-independent corrector circuitry including
frequency-independent phase correction circuitry responsive to the DSA control signal to introduce a DSA phase correction to correct for the frequency-independent DSA phase errors; and
frequency-independent gain correction circuitry responsive to the DSA control signal to introduce frequency-independent gain correction to correct for the frequency-independent gain errors.

8. The circuit of claim 7 , further comprising:
a digital downconverter (DDC) in the digital signal path to downconvert the digital ADC output to the baseband frequency, the DDC including:
a mixer coupled to the ADC, and
a numerical controlled oscillator (NCO) to drive the mixer with an time-varying NCO phase signal, and
a decimation filter chain coupled to the mixer;

the frequency-independent phase correction circuitry coupled to the NCO, and responsive to the DSA control signal to add a DSA phase correction to the NCO phase signal to correct frequency-independent DSA phase errors.

9. The circuit of claim 8 , wherein the parameterized filter has a filter response in the frequency domain that is linear across frequency, and further comprising a calibration operation in which, for each DSA attenuation step:
for the DSA frequency-dependent corrector filter, the complex filter parameter for the parameterized filter is determined based on responses of the DSA to two tone signals in the target frequency band, with a slope of the DSA responses equated to the slope of the linear phase change of the parameterized filter, and the slope of the linear gain change of the parameterized filter, over the pre-defined frequency range, to correct frequency-dependent DSA phase and gain errors; and
for the DSA frequency-independent corrector circuitry, the DSA phase correction to correct frequency-independent DSA phase errors, and the DSA gain correction to correct frequency-independent DSA gain errors, are estimated based on residual frequency-independent DSA phase error and frequency-independent DSA gain error remaining after the DSA frequency-dependent corrector filter has corrected frequency-dependent phase and gain errors.

10. The circuit of claim 9 , wherein:
for each DSA attenuation step, the DSA control signal is a control word; and
the associated complex filter parameter for the parameterized filter to correct frequency-dependent phase and gain errors is stored in a look-up-table, addressed by the DSA control word;
the associated frequency-independent DSA phase correction is stored in a look-up-table, addressed by the DSA control word; and
the associated frequency-independent DSA gain correction is stored in a look-up-table, addressed by the DSA control signal.

11. The circuit of claim 1 , wherein the DSA is integrated into the analog signal path.

12. A circuit for correcting frequency-dependent errors in a digital step attenuator (DSA), comprising:
analog circuitry to provide an analog signal in an analog signal path;
DSA circuitry configured to attenuate the analog signal with selectable DSA attenuation steps based on a DSA control signal, and generate a DSA output that includes, for at least some of the DSA attenuation steps, DSA phase errors and/or DSA gain errors;
an analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path;
the ADC configured to convert an input signal corresponding to the DSA output to a digital ADC output provided to the digital signal path;
a DSA frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with a complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

13. The circuit of claim 12 , wherein:
the parameterized filter has a filter response in the frequency domain that is linear across frequency; and
the complex filter parameter having a real part determining a slope of the linear phase change response of the parameterized filter over a pre-defined frequency range within the target frequency band to correct the frequency-dependent DSA phase error, and/or an imaginary part determining a slope of the linear gain change response of the parameterized filter over a pre-defined frequency range within the target frequency band to correct the frequency-dependen

Assignees

• Texas Instruments Inc

Inventors

• Tangudu Jawaharlal
• Khanna S Karthik
• Sriram Chandrasekhar
• Joish Rajendrakumar
• Nagarajan Viswanathan

Classifications

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03H11/1204 Primary

  Distributed RC filters · CPC title

• H03H2011/0494

  Complex filters · CPC title

• H01P1/22

  Attenuating devices (dissipative terminating devices H01P1/26) · CPC title

• H03H11/06

  comprising means for compensation of loss · CPC title