Current compliance layers and memory arrays comprising thereof

Patent metadata

Field	Value
Publication number	US-10580978-B2
Application number	US-201815863199-A
Country	US
Kind code	B2
Filing date	Jan 5, 2018
Priority date	Jan 8, 2017
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.

First claim

What is claimed is:

1. A memory device, comprising:
a current compliance layer (CCL), the CCL comprising an interface layer and a main layer,
wherein the interface layer directly interfaces the main layer,
wherein the interface layer comprises tellurium oxide,
wherein the main layer comprises germanium and tellurium; and

a memory element, wherein the CCL is stacked with and connected in series with the memory element.

2. The memory device of claim 1 , wherein a concentration of germanium varies throughout a thickness of the main layer, the thickness extending in a direction substantially perpendicular to an interface between the main layer and the interface layer.

3. The memory device of claim 2 , wherein the concentration of germanium in the main layer increases toward the interface between the main layer and the interface layer.

4. The memory device of claim 2 , wherein the concentration of germanium in the main layer has multiple spikes throughout the thickness of the main layer.

5. The memory device of claim 1 , wherein a concentration of tellurium in the main layer is between about 80% atomic and 99% atomic.

6. The memory device of claim 1 , wherein a concentration of germanium in the main layer is between about 1% atomic and 10% atomic.

7. The memory device of claim 1 , wherein a thickness of the interface layer is between about 0.1 nanometers and 10 nanometers.

8. The memory device of claim 1 , wherein the interface layer is substantially conformal.

9. The memory device of claim 1 , wherein a thickness of the main layer is between about 10 nanometers and 200 nanometers.

10. The memory device of claim 1 , wherein the CCL further comprises a first electrode, wherein the interface layer is disposed between the first electrode and the main layer, and wherein the interface layer directly interfaces the first electrode.

11. The memory device of claim 10 , wherein the CCL further comprises a second electrode, wherein the main layer is disposed between the second electrode and the interface layer, and wherein the main layer directly interfaces the second electrode.

12. The memory device of claim 1 , wherein the memory element directly interfaces the main layer of the CCL.

13. The memory device of claim, wherein the memory element is a ReRAM.

14. The memory device of claim 1 , wherein the memory element includes a variable resistance layer.

Assignees

• Intermolecular Inc

Inventors

• Chiang Tony
• Barabash Sergey V
• Littau Karl
• Narasimhan Vijay Kris
• Weeks Stephen

Classifications

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• G11C13/003 Primary

  Cell access · CPC title

• H01L45/1608

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic