Wafer level packaging method

Patent metadata

Field	Value
Publication number	US-10580823-B2
Application number	US-201715586102-A
Country	US
Kind code	B2
Filing date	May 3, 2017
Priority date	May 3, 2017
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

First claim

What is claimed is:

1. A wafer level packaging method, comprising:
bonding a first wafer over a second wafer;
performing a first grinding process on the first wafer, to remove an upper chamfered edge of the first wafer and reduce a first thickness of the first wafer;
performing a trimming process on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer, wherein the lower chamfered edge of the first wafer may be trimmed downwardly and stopped at the second wafer; and
performing a second grinding process on the trimmed first wafer, to reduce a second thickness of the trimmed first wafer in its entire width,
wherein a plurality of first conductive pads and a first insulating layer surrounding the plurality of first conductive pads are formed at a bottom surface of the first wafer, a plurality of second conductive pads and a second insulating layer surrounding the plurality of second conductive pads are formed at a top surface of the second wafer, and the first conductive pads are electrically connected with the second conductive pads.

2. The wafer level packaging method according to claim 1 , wherein the first grinding process is stopped between the upper chamfered edge and the lower chamfered edge.

3. The wafer level packaging method according to claim 1 , wherein a ratio of the first thickness with respect to the second thickness is ranged from 0.7 to 4.4.

4. The wafer level packaging method according to claim 3 , wherein the first thickness of the first wafer is 40% to 75% of an original thickness of the first wafer.

5. The wafer level packaging method according to claim 3 , wherein the second thickness of the trimmed first wafer is 17% to 58% of an original thickness of the first wafer.

6. The wafer level packaging method according to claim 1 , wherein the first grinding process and the second grinding process comprise a chemical mechanical polishing process respectively.

7. The wafer level packaging method according to claim 1 , wherein a removal rate of the first grinding process is higher than or equal to a removal rate of the second grinding process.

8. The wafer level packaging method according to claim 1 , wherein the second grinding process sequentially comprises a coarse grinding process and a fine grinding process.

9. The wafer level packaging method according to claim 8 , wherein a ratio of a removal rate of the coarse grinding process with respect to a removal rate of the fine grinding process is ranged from 1 to 20.

10. The wafer level packaging method according to claim 1 , wherein a method of performing the trimming process comprises applying a mechanical method, wherein the trimming process is directly performed on the first wafer to remove the lower chamfered edge of the first wafer to form the trimmed first wafer directly after the first grinding process.

11. The wafer level packaging method according to claim 1 , wherein a trimmed width from an outermost edge of the first wafer by the trimming process is ranged from 3.5 mm to 8.5 mm.

12. The wafer level packaging method according to claim 1 , further comprising performing an etching process on the trimmed first wafer after the second grinding process.

13. A wafer level packaging method, comprising:
bonding a first device wafer over a second device wafer;
performing a first thinning process, to remove an upper chamfered edge of the first device wafer, and reduce a first thickness of the first device wafer;
performing a trimming process, to remove a lower chamfered edge of the first device wafer to form a trimmed first device wafer, wherein the lower chamfered edge of the first wafer may be trimmed downwardly and stopped at the second wafer; and
performing a second thinning process, to reduce a second thickness of the trimmed first device wafer, so that the trimmed first device wafer in entire width is thinned down to a third thickness,
wherein a plurality of first conductive pads and a first insulating layer surrounding the plurality of first conductive pads are formed at a bottom surface of the first device wafer, a plurality of second conductive pads and a second insulating layer surrounding the plurality of second conductive pads are formed at a top surface of the second device wafer, and the first conductive pads are electrically connected with the second conductive pads.

14. The wafer level packaging method according to claim 13 , wherein the first thinning process and the second thinning process respectively comprise a chemical mechanical polishing process.

15. The wafer level packaging method according to claim 13 , wherein the first thinning process is stopped between the upper chamfered edge and the lower chamfered edge.

16. A wafer level packaging method, comprising:
hybrid bonding a first device wafer over a second device wafer;
performing a first grinding process, to remove an upper chamfered edge of the first device wafer, and reduce a first thickness of the first device wafer;
performing a trimming process, to remove a lower chamfered edge of the first device wafer to form a trimmed first device wafer, wherein the lower chamfered edge of the first wafer may be trimmed downwardly and stopped at the second wafer; and
performing a second grinding process, to reduce a second thickness of the trimmed first device wafer, so that the trimmed first device wafer in entire width is thinned down to a third thickness,
wherein a plurality of first conductive pads and a first insulating layer surrounding the plurality of first conductive pads are formed at a bottom surface of the first device wafer, a plurality of second conductive pads and a second insulating layer surrounding the plurality of second conductive pads are formed at a top surface of the second device wafer, and the first conductive pads are electrically connected with the second conductive pads.

17. The wafer level packaging method according to claim 16 , wherein the first device wafer and the second device wafer comprise a CMOS image sensor wafer or an image signal processor wafer.

18. The wafer level packaging method according to claim 16 , wherein the step of hybrid bonding the first device wafer over the second device wafer comprises contacting the first insulating layer over the second insulating layer, then performing a heat treatment to electrically connect the first conductive pads with the second conductive pads.

19. The wafer level packaging method according to claim 16 , further comprising sequentially forming a color filter and a plurality of micro lens on the first device wafer after the second grinding process.

Assignees

• United Microelectronics Corp

Inventors

• Zhang Sheng
• Ding Wen-Bo
• Sheng Zhi-Rui
• Hsu Chien-En
• Pang Chien-Kee

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H01L27/1469 Primary

  Electricity · mapped topic

• H01L27/14685

  Electricity · mapped topic

• H01L2924/10272

  Electricity · mapped topic

• H01L2224/8084

  Electricity · mapped topic