Method for manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-10580753-B2
Application number	US-201715656388-A
Country	US
Kind code	B2
Filing date	Jul 21, 2017
Priority date	Jul 21, 2017
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

According to an embodiment of a method of manufacturing a plurality of semiconductor devices on a wafer, the method includes forming a structure layer comprising a plurality of same semiconductor device structures and providing a protective layer on the structure layer. The protective layer on a first one of the plurality of semiconductor device structures differs from the protective layer on a second one of the plurality of semiconductor device structures.

First claim

The invention claimed is:

1. A method of manufacturing a plurality of semiconductor devices on a wafer, the method comprising:
forming a structure layer comprising a plurality of semiconductor device structures, wherein the semiconductor device structures include a conductive line that can be changed to an interrupted conductive line, or include the interrupted conductive line that can be changed to the conductive line, wherein the conductive line and the interrupted conductive line each include a first metal line and a second metal line formed on a surface of a substrate of the wafer, the first metal line having a first terminal end and the second metal line having a second terminal end, wherein the first terminal end and the second terminal end are separated by a gap;
forming a base protective layer having a plurality of same openings above the first terminal end of the first metal line and the second terminal end of the second metal line for the conductive line and the interrupted conductive line for the plurality of semiconductor devices, wherein for the conductive line, the first metal line is conductively coupled to the second metal line within the opening, and wherein for the interrupted conductive line, the current flow is impeded by the gap between the first metal line and the second metal line within the opening;
providing a protective substance on the structure layer, wherein the protective substance prevents the change in the conductive line to the interrupted conductive line, or in the interrupted conductive line to the conductive line,
wherein the protective substance on a first one of the plurality of semiconductor device structures differs from the protective substance on a second one of the plurality of semiconductor device structures; and
applying a configuring substance on the protective substance and the structure layer, wherein, for the first one of the plurality of semiconductor device structures, the configuring substance causes the interrupted conductive line to be changed to the conductive line, or causes the conductive line to be changed to the interrupted conductive line.

2. The method of claim 1 ,
wherein the first one of the plurality of semiconductor device structures is associated with a first one of the plurality of semiconductor devices and the second one of the plurality of semiconductor device structures is associated with a second one of the plurality of semiconductor devices which is separate from the first one of the plurality of semiconductor devices, and
wherein the first one of the plurality of semiconductor device structures and the second one of the plurality of semiconductor device structures have a same device geometry.

3. The method of claim 2 , wherein the protective substance is a passivating substance.

4. The method of claim 1 , wherein providing the protective substance comprises:
selectively depositing the protective substance within the opening of the base protective layer.

5. The method of claim 4 , the method further comprising:
generating a data file for use in control of a dispensing device configured to dispense the protective substance.

6. The method of claim 4 , the method further comprising:
testing the plurality of semiconductor device structures.

7. The method of claim 6 , the method further comprising:
based on a test result, deriving a selected circuit element on the wafer to be configured.

8. A The method of claim 7 , wherein the selected circuit element comprises the conductive line.

9. The method of claim 7 , wherein the selected circuit element comprises the interrupted conductive line.

10. The method of claim 1 , wherein the configuring substance comprises one or more reactants from a group of reactants consisting of an etchant, a solvent, an oxidizing agent and a complex-forming agent.

11. The method of claim 10 , wherein the protective substance is configured to resist the one or more reactants.

12. The method of claim 11 , wherein the protective layer is a photo resist layer.

13. The method of claim 1 , wherein the configuring substance is conductive.

14. The method of claim 1 , wherein the configuring substance is configured to become conductive when provided in the opening of the base protective layer.

15. The method of claim 1 , wherein the configuring substance comprises a metal.

16. The method of claim 1 , wherein the protective layer is a passivation layer.

Assignees

• Infineon Technologies Ag

Inventors

• Mischitz Martin
• Huber Harald
• Knabl Michael
• Sgiarovello Claudia
• Travan Caterina
• Wood Andrew

Classifications

• H01L25/50

  Electricity · mapped topic

• H01L23/3171

  Electricity · mapped topic

• H01L24/94 Primary

  Electricity · mapped topic

• H01L25/0655

  Electricity · mapped topic

• H01L23/525

  Electricity · mapped topic