Microprocessor for gating a load operation based on entries of a prediction table

Patent metadata

Field	Value
Publication number	US-10579386-B2
Application number	US-201816217628-A
Country	US
Kind code	B2
Filing date	Dec 12, 2018
Priority date	Mar 15, 2013
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

An apparatus for gating a load instruction is presented. The apparatus includes a memory to store a prediction table including an entry matching the load instruction. The matching entry includes a tag field to identify the load instruction, a distance field to indicate a distance of the load instruction to a prior aliasing store instruction, and a confidence field to indicate a prediction strength. The apparatus further includes a gating circuit operable to perform a look-up for the load instruction in the prediction table to find the matching entry and responsive to a determination of a valid prediction, retrieve a location of the prior aliasing store instruction using a value of the distance field of the matching entry, and perform a gating operation on the load instruction. The apparatus further includes a load store queue operable to provide feedback for updating the matching entry after the load instruction has executed.

First claim

What is claimed is:

1. An apparatus for gating a load instruction, said apparatus comprising:
a memory to store a prediction table comprising a plurality of entries including a matching entry matching said load instruction, wherein said matching entry comprises:
a tag field to identify said load instruction,
a distance field to indicate a distance of said load instruction to a prior aliasing store instruction, and
a confidence field to indicate a prediction strength;

a gating circuit operable to:
perform a look-up for said load instruction in said prediction table to find said matching entry,
determine if said matching entry provides a valid prediction by comparing a value of said confidence field of said matching entry with a threshold value,
responsive to a determination of a valid prediction, retrieve a location of said prior aliasing store instruction using a value of said distance field of said matching entry, and
perform a gating operation on said load instruction, wherein said gating operation prevents dispatching of said load instruction; and

a load store queue operable to provide feedback for updating said matching entry after said load instruction has executed, wherein said feedback is provided responsive to a determination that said matching entry provided a valid prediction and a determination that there is no forwarding to said load instruction from any store instruction, wherein said determination that said matching entry provided a valid prediction is made based on a hit indicator passed along a microprocessor pipeline to said load store queue, and wherein said feedback comprises distance information that indicates that there is no forwarding to said load instruction from any store instruction.

2. The apparatus of claim 1 , wherein said prediction table is instantiated within a scheduler of said microprocessor pipeline.

3. The apparatus of claim 1 , wherein
said feedback is provided from a memory stage of said microprocessor pipeline.

4. The apparatus of claim 1 , wherein said gating operation prevents dispatching of said load instruction until said prior aliasing store instruction has executed.

5. The apparatus of claim 1 , wherein said gating circuit is further operable to increment the value of said confidence field of said matching entry responsive to a determination that values of said tag field and said distance field of said matching entry match tag and distance information of said load instruction.

6. The apparatus of claim 1 , wherein said gating circuit is further configured to decrement the value of said confidence field of said matching entry in response to a determination that values of said tag field and said distance field of said matching entry do not match tag and distance information of said load instruction.

7. The apparatus of claim 1 , wherein a value of said tag field is generated using a Program Counter (PC) value of said load instruction.

8. The apparatus of claim 1 , wherein said value of said distance field is calculated by subtracting a Reorder Buffer Identification of said prior aliasing store instruction from a Reorder Buffer Identification of said load instruction.

9. The apparatus of claim 1 , further comprising:
a second gating circuit operable to:
perform a look-up for a second load instruction in a second prediction table to find a second matching entry matching said second load instruction, wherein said second matching entry indicates a location of a second prior aliasing store instruction; and
perform a second gating operation on said second load instruction using information from said second matching entry, wherein said second gating operation delays a data return of said second load instruction until said second prior aliasing store instruction forwards data to said second load instruction.

10. A set of one or more non-transitory computer readable storage media storing instructions, which when executed by a microprocessor, causes said microprocessor to perform operations for gating a load instruction, said operations comprising:
performing a look-up for said load instruction in a prediction table to find a matching entry, wherein said matching entry comprises:
a tag field to identify said load instruction,
a distance field to indicate a distance of said load instruction to a prior aliasing store instruction, and
a confidence field to indicate a prediction strength;

determining if said matching entry provides a valid prediction by comparing a value of said confidence field with a threshold value;
responsive to a determination of a valid prediction, retrieving a location of said prior aliasing store instruction using a value of said distance field; and
performing a gating operation on said load instruction, wherein said gating operation prevents dispatching of said load instruction; and
updating said matching entry after said load instruction has executed by providing feedback from a load store queue responsive to a determination that said matching entry provided a valid prediction and a determination that there is no forwarding to said load instruction from any store instruction, wherein said determination that said matching entry provided a valid prediction is made based on a hit indicator passed along a microprocessor pipeline to said load store queue, and wherein said feedback includes distance information that indicates that there is no forwarding to said load instruction from any store instruction.

11. The set of one or more non-transitory computer readable storage media of claim 10 , wherein said performing a look-up, said determining if said matching entry provides a valid prediction, said retrieving a location of said prior aliasing store instruction, and said performing a gating operation are executed within a scheduler of said microprocessor pipeline.

12. The set of one or more non-transitory computer readable storage media of claim 10 , wherein said gating operation prevents dispatching of said load instruction until said prior aliasing store instruction has executed.

13. The set of one or more non-transitory computer readable storage media of claim 10 , wherein
said feedback is provided from said load store queue in a memory stage of said microprocessor pipeline.

14. The set of one or more non-transitory computer readable storage media of claim 10 , wherein said operations further comprise:
incrementing the value of said confidence field of said matching entry in response to a determination that values of said tag field and said distance field of said matching entry match tag and distance information of said load instruction.

15. The set of one or more non-transitory computer readable storage media of claim 10 , wherein said operations further comprise:
decrementing the value of said confidence field of said matching entry in response to a determination that values of said tag field and said distance field of said matching entry do not match tag and distance information of said load instruction.

16. The set of one or more non-transitory computer readable storage media of claim 10 , wherein a value of said tag field is generated using a Program Counter (PC) value of said load instruction.

17. The set of one or more non-transitory computer readable storage media of claim 10 , wherein said value of said distance field is calculated by subtracting a Reorder Buffer Identification of said prior aliasing store instruction from a Reorder Buffer Identification of said load instruction.

18. The set of one or more non-transitory computer readable storage claim 10 , wherein

Assignees

• Intel Corp

Inventors

• Zeng Hui

Classifications

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title