Apparatus for gating a load operation based on entries of a prediction table

Patent metadata

Field	Value
Publication number	US-10152327-B2
Application number	US-201314063409-A
Country	US
Kind code	B2
Filing date	Oct 25, 2013
Priority date	Mar 15, 2013
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

An apparatus for gating a load operation is presented. The apparatus comprises a memory resident data structure, wherein the memory resident data structure is a prediction table comprising a plurality of entries, wherein a matching entry corresponding to the load operation within the prediction table comprises a prediction regarding a dependence of the load operation on a prior aliasing store instruction, and wherein the matching entry comprises: (a) a tag field operable to identify the matching entry; (b) a distance field operable to indicate a distance of the load operation to the prior aliasing store instruction; and (c) a confidence field operable to indicate a prediction strength generated by the prediction table, wherein the prediction strength influences a gating of the load operation.

First claim

What is claimed is:

1. An apparatus for gating a load operation, said apparatus comprising:
a memory resident data structure, wherein said memory resident data structure is a prediction table comprising a plurality of entries residing in a memory stage of a microprocessor pipeline, wherein a matching entry corresponding to said load operation within said prediction table comprises a prediction regarding a dependence of said load operation on a prior aliasing store instruction, and wherein said matching entry comprises:
a composite tag field operable to identify said matching entry, wherein a value of said composite tag field is generated using a Program Counter (PC) value of said load operation, a thread identifier, and a distance of said load operation to a most recent prior store on a control path leading to said load operation,
a distance field operable to indicate a distance of said load operation to said prior aliasing store instruction, and
a confidence field operable to indicate a prediction strength, wherein said prediction strength influences a gating of said load operation; and

a gating circuit in said memory stage of said microprocessor pipeline configured to:
perform a look-up for said load operation in said prediction table to find said matching entry;
determine if said matching entry provides a valid prediction by comparing a value of said confidence field for said matching entry with a threshold value;
responsive to a determination of a valid prediction, retrieve a location for said prior aliasing store instruction using a value of said distance field; and
perform a gating operation on said load operation, wherein said gating operation delays a data return of said load operation, and wherein said load operation is delayed until said prior aliasing store instruction forwards data to said load operation.

2. The apparatus of claim 1 , wherein said gating circuit is further configured to increment the value of said confidence field in said prediction table in response to a determination that said composite tag field and said distance field of said matching entry match tag and distance information of said load operation.

Assignees

• Intel Corp

Inventors

• Zeng Hui

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title