Method and apparatus for a scalable interrupt infrastructure

Patent metadata

Field	Value
Publication number	US-10579382-B2
Application number	US-201815879416-A
Country	US
Kind code	B2
Filing date	Jan 24, 2018
Priority date	Jan 24, 2018
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

An apparatus and method for scalable interrupt reporting. For example, one embodiment of an apparatus comprises: a host processor to execute one or more processes having a corresponding one or more process contexts associated therewith; and a graphics processing engine to, upon initiating execution of a first process, determine a current process context associated with the first process including a first pointer to a first system memory region to store an interrupt status, a second pointer to a second system memory region to store interrupt enable and/or interrupt mask data for one or more interrupt events, and address/data values associated with a message signaled interrupt (MSI); the graphics processing engine, in response to an interrupt event, to evaluate the interrupt enable data from the second system memory region to determine whether the interrupt event is enabled, to report the interrupt event, if enabled, by writing a specified value to the first system memory region identified by the first pointer, and to generate a first MSI corresponding to the interrupt event by writing the MSI address/data values to an output accessible by the host processor.

First claim

What is claimed is:

1. A graphics processing apparatus comprising:
a host processor to execute one or more processes having a corresponding one or more process contexts associated therewith; and
a graphics processing engine to, upon initiating execution of a first process, determine a current process context associated with the first process including a first pointer to a first system memory region to store an interrupt status, a second pointer to a second system memory region to store interrupt enable and/or interrupt mask data for one or more interrupt events, and address/data values associated with a message signaled interrupt (MSI);
the graphics processing engine, in response to an interrupt event, to evaluate the interrupt enable data from the second system memory region to determine whether the interrupt event is enabled, to report the interrupt event, if enabled, by writing a specified value to the first system memory region identified by the first pointer, and to generate a first MSI corresponding to the interrupt event by writing the MSI address/data values to an output accessible by the host processor.

2. The apparatus of claim 1 wherein the one or more processes comprise one or more virtual machines (VMs) and/or one or more applications.

3. The apparatus of claim 1 wherein one or more of the processes executed on the host processor use atomics to read and write interrupt status information in memory.

4. The apparatus of claim 3 wherein the host processor comprises a general purpose central processing unit (CPU) and the graphics processing engine comprises a graphics processing unit (GPU), wherein the use of atomics by the CPU avoids the loss of graphics engine updates resulting from read-modify-write of the interrupt status in memory.

5. The apparatus of claim 1 wherein the first interrupt is directed to one or more virtual machines and/or applications to be executed on the host processor.

6. The apparatus of claim 1 wherein the current process context comprises a process address space ID (PASID) value to uniquely identify the first process.

7. The apparatus of claim 6 wherein the current process context further comprises a per-page graphics translation table (PP-GTT) pointer to identify a page table associated with the first process, the page table to be used to perform address translations for the first process.

8. The apparatus of claim 1 wherein an opcode associated with the MSI is transmitted over an on-die interface (IDI) link to one or more processing devices.

9. A method comprising:
determining a process context associated with a first process of a plurality of processes, the process context including a first pointer to a first system memory region to store an interrupt status, a second pointer to a second system memory region to store interrupt enable and/or interrupt mask data for one or more interrupt events, and address/data values associated with a message signaled interrupt (MSI);
detecting an interrupt event;
reading the interrupt enable data from the second system memory region;
determining whether the interrupt event is enabled based on the interrupt enable data;
reporting the interrupt event, if enabled, by writing a specified value to the first system memory region identified by the first pointer; and
generating a first interrupt corresponding to the interrupt event using the MSI address/data values.

10. The method of claim 9 wherein the plurality of processes include one or more virtual machines (VMs) and/or one or more applications executed on a host processor.

11. The method of claim 10 wherein one or more of the processes executed on the host processor use atomics to read and write interrupt status information in memory.

12. The method of claim 11 wherein the host processor comprises a general purpose central processing unit (CPU) and operations of determining a process context, detecting an interrupt event, reading the interrupt enable data, determining whether the interrupt event is enabled, reporting the interrupt event, and generating the first interrupt are performed by a graphics processing engine.

13. The method of claim 12 wherein the use of atomics by the CPU avoids the loss of graphics engine updates resulting from read-modify-write of the interrupt status in memory.

14. The method of claim 10 wherein the first interrupt is directed to the one or more virtual machines and/or applications executed on the host processor.

15. The method of claim 9 wherein the current process context comprises a process address space ID (PASID) value to uniquely identify the first process.

16. The method of claim 15 wherein the current process context further comprises a per-page graphics translation table (PP-GTT) pointer to identify a page table associated with the first process, the page table to be used to perform address translations for the first process.

17. The method of claim 15 wherein an opcode associated with the MSI is transmitted over an on-die interface (IDI) link to one or more processing devices.

18. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
determining a process context associated with a first process of a plurality of processes, the process context including a first pointer to a first system memory region to store an interrupt status, a second pointer to a second system memory region to store interrupt enable and/or interrupt mask data for one or more interrupt events, and address/data values associated with a message signaled interrupt (MSI);
detecting an interrupt event;

reading the interrupt enable data from the second system memory region;
determining whether the interrupt event is enabled based on the interrupt enable data;
reporting the interrupt event, if enabled, by writing a specified value to the first system memory region identified by the first pointer; and
generating a first interrupt corresponding to the interrupt event using the MSI address/data values.

19. The non-transitory machine-readable medium of claim 18 wherein the plurality of processes include one or more virtual machines (VMs) and/or one or more applications executed on a host processor.

20. The non-transitory machine-readable medium of claim 19 wherein one or more of the processes executed on the host processor use atomics to read and write interrupt status information in memory.

21. The non-transitory machine-readable medium of claim 20 wherein the host processor comprises a general purpose central processing unit (CPU) and operations of determining a process context, detecting an interrupt event, reading the interrupt enable data, determining whether the interrupt event is enabled, reporting the interrupt event, and generating the first interrupt are performed by a graphics processing engine.

22. The non-transitory machine-readable medium of claim 21 wherein the use of atomics by the CPU avoids the loss of graphics engine updates resulting from read-modify-write of the interrupt status in memory.

23. The non-transitory machine-readable medium of claim 19 wherein the first interrupt is directed to the one or more virtual machines and/or applications executed on the host processor.

24. The non-transitory machine-readable medium of claim 18 wherein the current process context comprises a process address space ID (PASID) value to uniquely identify the first process.

Assignees

• Intel Corp

Inventors

• Sankaran Rajesh
• Shah Ankur
• White Bryan
• Nalluri Hema
• Puffer David
• Ramadoss Murali
• Koker Altug
• Navale Aditya
• Vembu Balaji

Classifications

• G06F2209/544

  Remote · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F2212/455

  Image or video data · CPC title