Co-fabricated gate-all-around field effect transistor and fin field effect transistor

Patent metadata

Field	Value
Publication number	US-10566434-B2
Application number	US-201715853136-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Dec 22, 2016
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

The disclosed technology generally relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to semiconductor structures related to a gate-all-around field effect transistor and a fin field effect transistor. In one aspect, a method of forming field effect transistors includes forming in a first region of a substrate a first semiconductor feature and forming in a second region of the substrate a second semiconductor feature. Each of the first and second semiconductor features comprises a fin-shaped semiconductor feature including a vertical stack of at least a first semiconductor material layer and a second semiconductor material layer formed over the first semiconductor material layer. The method additionally includes selectively etching to remove the first semiconductor material layer along a longitudinal section of the first semiconductor feature to form a suspended longitudinal first semiconductor feature of a remaining second semiconductor material layer, while masking the second region to prevent etching of the second semiconductor feature. The method additionally includes forming a gate-all-around electrode surrounding the suspended longitudinal first semiconductor feature in the first region. The method further includes forming a gate electrode on the fin-shaped second semiconductor feature in the second region.

First claim

What is claimed is:

1. A method of forming field effect transistors, the method comprising:
forming in a first region of a substrate a first semiconductor feature and forming in a second region of the substrate a second semiconductor feature, wherein each of the first and second semiconductor features is formed in a dielectric layer and comprises a fin-shaped semiconductor feature including a vertical stack of at least a first semiconductor material layer and a second semiconductor material layer formed over the first semiconductor material layer;
forming a first sacrificial gate stack including a sacrificial gate and a sacrificial gate dielectric on a longitudinal section of the first semiconductor feature;
forming a second sacrificial gate stack including a sacrificial gate and a sacrificial gate dielectric on a longitudinal section of the second semiconductor feature;
removing the sacrificial gate of the first sacrificial gate stack and the sacrificial gate of the second sacrificial gate stack, thereby forming a first trench and a second trench in the dielectric layer, the first trench exposing the sacrificial gate dielectric along the longitudinal section of the first semiconductor feature and the second trench exposing the sacrificial gate dielectric along the longitudinal section of the second semiconductor feature;
forming a mask over the second trench;
removing the sacrificial gate dielectric in the first trench, thereby exposing the longitudinal section of the first semiconductor feature in the first trench, wherein the mask formed over the second trench prevents etching of the sacrificial gate dielectric in the second trench during the removal of the sacrificial gate dielectric in the first trench;
selectively etching to remove the first semiconductor material layer along the longitudinal section of the first semiconductor feature to form a suspended longitudinal first semiconductor feature of a remaining second semiconductor material layer, while masking the second region to prevent etching of the second semiconductor feature;
forming a gate-all-around electrode surrounding the suspended longitudinal first semiconductor feature in the first region; and
forming a gate electrode on the fin-shaped second semiconductor feature in the second region.

2. The method according to claim 1 , wherein forming the gate-all-around electrode on the suspended longitudinal first semiconductor feature includes depositing a first gate conductor in the first trench, and wherein forming the gate electrode on the fin-shaped second semiconductor feature includes depositing a second gate conductor in the second trench.

3. A method of forming field effect transistors, the method comprising:
forming in a first region of a substrate a first semiconductor feature and forming in a second region of the substrate a second semiconductor feature, wherein each of the first and second semiconductor features is formed in a dielectric layer and comprises a fin-shaped semiconductor feature including a vertical stack of at least a first semiconductor material layer and a second semiconductor material layer formed over the first semiconductor material layer;
forming a first sacrificial gate stack including a sacrificial gate and a sacrificial gate dielectric on a longitudinal section of the first semiconductor feature;
forming a second sacrificial gate stack including a sacrificial gate and a sacrificial gate dielectric on a longitudinal section of the second semiconductor feature;
removing the sacrificial gate of the first sacrificial gate stack and the sacrificial gate of the second sacrificial gate stack, thereby forming a first trench and a second trench in the dielectric layer, the first trench exposing the sacrificial gate dielectric along the longitudinal section of the first semiconductor feature and the second trench exposing the sacrificial gate dielectric along the longitudinal section of the second semiconductor feature;
removing the sacrificial gate dielectric in the first trench, thereby exposing the longitudinal section of the first semiconductor feature in the first trench;
selectively etching to remove the first semiconductor material layer along the longitudinal section of the first semiconductor feature to form a suspended longitudinal first semiconductor feature of a remaining second semiconductor material layer, while masking the second region to prevent etching of the second semiconductor feature;
subsequent to forming the suspended longitudinal first semiconductor feature in the first trench, removing the sacrificial gate dielectric in the second trench;
forming a gate-all-around electrode surrounding the suspended longitudinal first semiconductor feature in the first region; and
forming a gate electrode on the fin-shaped second semiconductor feature in the second region.

4. The method according to claim 1 , further comprising, prior to forming the gate-all-around electrode and the gate electrode, depositing a gate dielectric in the first trench on the longitudinal section of the suspended longitudinal first semiconductor feature.

5. The method according to claim 1 , further comprising, prior to forming the gate-all-around electrode and the gate electrode, depositing a gate dielectric in the second trench on the longitudinal section of the second semiconductor feature.

6. The method according to claim 1 , wherein the first semiconductor material layer is formed of a SiGe-based material and the second semiconductor material layer is formed of a Si-based material.

7. The method according to claim 1 , wherein the first semiconductor material layer is formed of a Si-based material and the second semiconductor material layer is formed of a SiGe-based material.

8. The method according to claim 1 , further comprising forming source and drain regions in the first semiconductor feature to form a gate-all-around field effect transistor (GAAFET), and forming source and drain regions in the second semiconductor feature to form a fin field effect transistor (FinFET).

9. The method according to claim 3 , wherein forming the gate-all-around electrode on the suspended longitudinal first semiconductor feature includes depositing a first gate conductor in the first trench, and wherein forming the gate electrode on the fin-shaped second semiconductor feature includes depositing a second gate conductor in the second trench.

10. The method according to claim 3 , further comprising, prior to forming the gate-all-around electrode and the gate electrode, depositing a gate dielectric in the first trench on the longitudinal section of the suspended longitudinal first semiconductor feature.

11. The method according to claim 3 , further comprising, prior to forming the gate-all-around electrode and the gate electrode, depositing a gate dielectric in the second trench on the longitudinal section of the second semiconductor feature.

12. The method according to claim 3 , wherein the first semiconductor material layer is formed of a SiGe-based material and the second semiconductor material layer is formed of a Si-based material.

13. The method according to claim 3 , wherein the first semiconductor material layer is formed of a Si-based material and the second semiconductor material layer is formed of a SiGe-based material.

14. The method according to claim 3 , further comprising forming source and drain regions in the first semiconductor feature to form a gate-all-around field effect transistor (GAAFET), and forming source and drain regions in the second semiconductor feature to form a fin field effect transistor (FinFET).

Assignees

• Imec Vzw

Inventors

• Hellings Geert

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L29/0673

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic