High bandwidth routing for die to die interposer and on-chip applications

Patent metadata

Field	Value
Publication number	US-10566286-B2
Application number	US-201916250854-A
Country	US
Kind code	B2
Filing date	Jan 17, 2019
Priority date	Dec 18, 2017
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads.

First claim

What is claimed is:

1. A routing structure comprising:
a first die area;
a second die area;
a signal routing connecting the first die area and the second die area, wherein the signal routing comprises:
a plurality of stacked reference lines extending between the first die area and the second die area;
a stacked signal line bundle extending between the first die area and the second die area;
one or more pads directly over the stacked signal line bundle, wherein the one or more pads have a polygonal shape with a vertex oriented orthogonal to the stacked signal line bundle.

2. The routing structure of claim 1 , wherein the stacked signal line bundle includes a plurality of inter-layer switch regions in which a signal path changes between a plurality of metal layers.

3. The routing structure of claim 2 , further comprising a vacated track region of an uppermost metal layer directly underneath the one or more pads and over the stacked signal line bundle.

4. The routing structure of claim 2 , further comprising one or more reference lines in an uppermost metal layer directly underneath the one or more pads and over the stacked signal line bundle.

5. The routing structure of claim 2 , wherein the stacked signal line bundle occupies an uppermost metal layer directly underneath the one or more pads.

6. The routing structure of claim 2 , wherein the signal routing is formed in a substrate that is separate from the first and second die areas, and the first and second die areas are discrete chips.

7. The routing structure of claim 2 , wherein the signal routing is formed on a same silicon layer as the first and second die areas, such that the signal routing, first die area, and second die area are part of a single chip.

8. The routing structure of claim 2 , wherein the stacked signal line bundle includes a plurality of stacked trace lines.

9. The routing structure of claim 8 , wherein at least one of the plurality of intra-layer switch regions comprises a signal line switching to a vacated reference line area.

10. The routing structure of claim 9 , wherein a first plurality of the inter-layer switch regions comprise first vias characterized by approximately a same width as a minimum line width of the stacked reference lines the corresponding vias connect.

11. The routing structure of claim 8 , wherein a second plurality of the inter-layer switch regions comprise second vias characterized by approximately a same width as a minimum line width of the stacked trace lines the corresponding vias connect.

12. The routing structure of claim 8 , wherein each of the stacked trace lines is characterized by a corresponding thickness that is greater than a width.

13. The routing structure of claim 1 , further comprising a capacitor adjacent the signal routing.

14. The routing structure of claim 1 , further comprising a vacated track region of an uppermost metal layer directly underneath the one or more pads and over the stacked signal line bundle.

15. The routing structure of claim 1 , wherein the stacked signal line bundle occupies an uppermost metal layer directly underneath the one or more pads.

16. The routing structure of claim 1 , further comprising one or more reference lines in an uppermost metal layer directly underneath the one or more pads and over the stacked signal line bundle.

17. The routing structure of claim 1 , wherein the signal routing is formed in a substrate that is separate from the first and second die areas, and the first and second die areas are discrete chips.

18. The routing structure of claim 1 , wherein the signal routing is formed on a same silicon layer as the first and second die areas, such that the signal routing, first die area, and second die area are part of a single chip.

19. The routing structure of claim 1 , wherein the stacked signal line bundle includes a plurality of stacked trace lines.

20. The routing structure of claim 19 , wherein each of the stacked trace lines is characterized by a corresponding thickness that is greater than a width.

Assignees

• Apple Inc

Inventors

• Dabral Sanjay
• Secker David A
• Chen Huabo
• Cheng Zhenggang

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title

• H10W72/01225

  in solid form, e.g. by using a powder or by stud bumping · CPC title