Hybrid logical to physical address translation for non-volatile storage devices with integrated compute module

Patent metadata

Field	Value
Publication number	US-10565123-B2
Application number	US-201715726313-A
Country	US
Kind code	B2
Filing date	Oct 5, 2017
Priority date	Apr 10, 2017
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A host compiles code to perform a set of one or more database operations on target and embeds an indication of whether the target data is randomly accessed data or sequentially accessed data. The compiled code is transmitted to the compute engine inside a memory system that maintains a first portion of memory for storing sequentially accessed data and a second portion of memory for storing randomly accessed data. The memory system (e.g. SSD) maintains reduced size L2P tables in volatile working memory by maintaining coarse L2P tables in the working memory for use with sequentially accessed data and maintaining fine L2P tables in the working memory for use with randomly accessed data. The compute engine uses the compiled code to perform the set of one or more database operations on the target data using the working memory.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory system, comprising:
non-volatile memory;
working memory separate from the non-volatile memory, the working memory is configured to store a coarse logical address to physical address table for use with data stored in the non-volatile memory as sequentially accessed data and a fine logical address to physical address table for use with data stored in the non-volatile memory as randomly accessed data;
a controller in communication with the non-volatile memory and the working memory, the controller includes a processor, the controller is configured to create data for the coarse logical address to physical address table by reading fine logical address to physical address data and reducing the fine logical address to physical address data to coarse logical address to physical address data, the controller is configured to:
randomly access data stored in the non-volatile memory as randomly accessed data in response to a request from a host by translating a logical address from the host to a physical address in the non-volatile memory using the fine logical address to physical address table in the working memory,
sequentially access data stored in the non-volatile memory as sequentially accessed data in response to a request from the host by translating a logical address from the host to a physical address in the non-volatile memory using the coarse logical address to physical address table in the working memory, and
randomly access data stored in the non-volatile memory as sequentially accessed data in response to a request from the host by translating a logical address from the host to a physical address in the non-volatile memory using the coarse logical address to physical address table in the working memory; and

a compute engine positioned within the memory system, the compute engine is in communication with the controller and the working memory, the compute engine is different than the processor included in the controller, the compute engine is configured to receive code from the host and perform one or more database operations on target data in the non-volatile memory by executing the code and using the working memory.

2. The apparatus of claim 1 , wherein:
the code received from the host is compiled code that includes an indication of whether the target data is sequentially accessed data or randomly accessed data.

3. The apparatus of claim 2 , wherein:
the controller includes a host interface;
the compute engine is behind the host interface;
the host interface is configured to receive the compiled code from the host and forward the compiled code to the compute engine; and
the compute engine is further configured to use the controller to perform address translation between logical and physical addresses for the target data based on the coarse logical address to physical address table and the fine logical address to physical address table in the working memory.

4. The apparatus of claim 1 , wherein:
the non-volatile memory includes a first portion of non-volatile memory configured to store sequentially accessed data comprising leaf node data for one or more database data structures and a second portion of non-volatile memory configured to store randomly accessed data comprising branch node data for one or more database data structures;
the controller is further configured to use the coarse logical address to physical address table to perform address translation between logical and physical addresses for sequentially accessed data stored in the first portion of non-volatile memory;
the controller is further configured to use the fine logical address to physical address table to perform address translation between logical and physical addresses for randomly accessed data stored in the second portion of non-volatile memory;
the coarse logical address to physical address table is separate from the leaf node data and the branch node data; and
the fine logical address to physical address table is separate from the leaf node data and the branch node data.

5. The apparatus of claim 1 , wherein:
the non-volatile memory includes a first portion of non-volatile memory configured to store sequentially accessed data comprising leaf node data for one or more database data structures and a second portion of non-volatile memory configured to store randomly accessed data comprising branch node data for one or more database data structures;
the coarse logical address to physical address table is separate from the leaf node data and the branch node data;
the fine logical address to physical address table is separate from the leaf node data and the branch node data;
the compute engine is further configured to use the coarse logical address to physical address table to perform address translation between logical and physical addresses for sequentially accessed data stored in the first portion of non-volatile memory; and
the compute engine is further configured to use the fine logical address to physical address table to perform address translation between logical and physical addresses for randomly accessed data stored in the second portion of non-volatile memory.

6. The apparatus of claim 1 , wherein:
the non-volatile memory includes a first portion of non-volatile memory configured to store leaf nodes of a database as sequentially accessed data and a second portion of non-volatile memory configured to store branch nodes of the database randomly accessed data;
the coarse logical address to physical address table is separate from the leaf nodes and the branch nodes;
the fine logical address to physical address table is separate from the leaf nodes and the branch nodes;
the compute engine is further configured to use the coarse logical address to physical address table to perform address translation between logical and physical addresses for the leaf nodes stored in the first portion of non-volatile memory; and
the compute engine is further configured to use the fine logical address to physical address table to perform address translation between logical and physical addresses for the branch nodes stored in the second portion of non-volatile memory.

7. The apparatus of claim 2 , wherein:
wherein the indication of whether the target data is sequentially accessed data or random accessed data is inferred from a type of the one or more database operations specified by the code.

8. The apparatus of claim 1 , wherein:
the working memory is volatile memory; and
the compute engine is further configured to use the volatile working memory to store working data for the compute engine while performing the one or more database operations.

9. The apparatus of claim 1 , wherein:
the non-volatile memory includes a memory package that is separate from and connected to the controller; and
the memory package includes one or more non-volatile memory dies and the compute engine.

10. The apparatus of claim 9 , wherein:
the compute engine is positioned on a first memory die of the one of the non-volatile memory dies;
the code received from the host is compiled code that is received by the compute engine on the first memory die; and
the compute engine is configured to execute the compiled code to access the target data on the first memory die based on
the coarse logical address to physical address table in the working memory for sequentially accessed data, and
the fine logical address to physical address table in the working memory for data randomly accessed data.

11. The apparatus of claim 1 , wherein:
the memory system is a solid state drive; and
the controller includes a host interface, the compute engine is in the solid state

Assignees

• Western Digital Tech Inc

Inventors

• Song Seung-Hwan
• De Arup
• Mehra Pankaj
• O'Krafka Brian W

Classifications

• G06F2212/1024

  Latency reduction · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title