Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10559580-B2
Application number	US-201615247602-A
Country	US
Kind code	B2
Filing date	Aug 25, 2016
Priority date	Oct 1, 2015
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a substrate;
insulating patterns and gate patterns alternately stacked on the substrate;
a channel structure that intersects the insulating patterns and the gate patterns and that is connected to the substrate;
a charge storage structure that is between the channel structure and the gate patterns; and
a contact structure that is on the substrate at a side of the insulating patterns and the gate patterns,
wherein at least one of the gate patterns comprises:
a first barrier pattern that is between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns that is adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region that is between a first portion of the first barrier pattern that extends along the first insulating pattern, a second portion of the first barrier pattern that extends along the second insulating pattern, and a third portion of the first barrier pattern that extends between the first portion and the second portion; and
a metal pattern that is in the concave region defined by the first barrier pattern and is between the third portion of the first barrier pattern and the charge storage structure.

2. The semiconductor memory device of claim 1 , wherein the at least one of the gate patterns further comprises:
a second barrier pattern that is in the concave region defined by the first barrier pattern,
wherein the second barrier pattern is between the metal pattern and the charge storage structure.

3. The semiconductor memory device of claim 1 , further comprising:
blocking patterns between the charge storage structure and respective ones of the metal patterns,
wherein the blocking patterns are spaced apart from each other by the insulating patterns in the first direction.

4. The semiconductor memory device of claim 3 , wherein the blocking patterns surround a portion of an outer sidewall of the charge storage structure.

5. The semiconductor memory device of claim 3 , wherein a first thickness of a respective one of the metal patterns in the first direction is smaller than a second thickness of a respective one of the blocking patterns in the first direction.

6. The semiconductor memory device of claim 1 , further comprising:
an insulating layer that is between the charge storage structure and the gate patterns,
wherein the insulating layer extends in the first direction.

7. The semiconductor memory device of claim 1 , wherein a sidewall of the metal pattern is laterally recessed from a sidewall of the first insulating pattern and a sidewall of the second insulating pattern to define an undercut region,
wherein the charge storage structure extends in the first direction, has a first segment between the channel structure and the metal pattern, and has second segments between the channel structure and the insulating patterns, and
wherein a portion of the first segment of the charge storage structure is in the undercut region.

8. The semiconductor memory device of claim 7 , wherein the channel structure comprises a portion that protrudes toward the metal pattern.

9. The semiconductor memory device of claim 1 , wherein the metal pattern comprises a first metal pattern, and the semiconductor memory device further comprises:
second metal patterns that are between the contact structure and respective first barrier patterns of the gate patterns, the second metal patterns spaced apart from each other in the first direction with one of the insulating patterns interposed between adjacent second metal patterns; and
an insulating layer that is between the first barrier patterns of the gate patterns and the second metal patterns, the insulating layer extending onto a top surface and a bottom surface of respective ones of the second metal patterns.

10. The semiconductor memory device of claim 1 , further comprising:
residual insulating patterns between the contact structure and respective first barrier patterns of the gate patterns, the residual insulating patterns spaced apart from each other in the first direction with one of the insulating patterns interposed between adjacent residual insulating patterns.

11. The semiconductor memory device of claim 10 , wherein a sidewall of at least one of the insulating patterns is in contact with the contact structure, and
wherein a sidewall of at least one of the residual insulating patterns is in contact with the contact structure.

12. The semiconductor memory device of claim 1 , wherein the metal pattern comprises a first metal pattern, and wherein the at least one of the gate patterns further comprises:
a second metal pattern that is between the first barrier pattern and the contact structure,
wherein one of the insulating patterns is interposed between adjacent ones of the second metal patterns.

13. A semiconductor memory device comprising:
a substrate;
a first gate pattern on the substrate;
second gate patterns that are sequentially stacked on the first gate pattern;
a semiconductor structure that is on the substrate, the semiconductor structure intersecting the first gate pattern;
a channel structure intersecting the second gate patterns and connected to the semiconductor structure;
a charge storage structure that is between the channel structure and the second gate patterns;
metal patterns on sidewalls of the second gate patterns, wherein the metal patterns are spaced apart from each other in a first direction perpendicular to a top surface of the substrate; and
an insulating layer that is between the second gate patterns and the metal patterns, the insulating layer extending onto a top surface and a bottom surface of respective ones of the metal patterns.

14. The semiconductor memory device of claim 13 , further comprising:
barrier patterns between the charge storage structure and the second gate patterns, wherein respective ones of the barrier patterns are spaced apart from each other in the first direction; and
blocking patterns between the charge storage structure and the barrier patterns, wherein respective ones of the blocking patterns are spaced apart from each other in the first direction.

15. The semiconductor memory device of claim 13 , further comprising:
barrier patterns between the insulating layer and respective ones of the second gate patterns, wherein respective ones of the barrier patterns extend onto a top surface and a bottom surface of respective ones of the second gate patterns.

16. A semiconductor memory device comprising:
a substrate;
a charge storage structure that is on the substrate and that extends in a first direction perpendicular to a main surface of the substrate;
a contact structure that is on the substrate and that extends in the first direction;
a plurality of insulating patterns that are stacked on the substrate in the first direction and that are between the charge storage structure and the contact structure in a second direction parallel to the main surface of the substrate;
a gate pattern that is on the substrate and that is between a first insulating pattern and a second insulating pattern of the plurality of insulating patterns that are adjacent one another in the first direction; and
a blocking pattern that is on the substrate and between the first insulating pattern and the second insulating pattern in the first direction, and that is between the gate pattern and the charge storage structure in the second direction,
wherein the gate patt

Assignees

• Son Yong Hoon
• Kim Kyunghyun
• Kim Byeongju
• Nam Phil Ouk
• PARK Kwangchul
• Sohn Yeon Sil
• Lee Jin I
• JUNG Wonbong
• Samsung Electronics Co Ltd

Inventors

• Son Yong-Hoon
• Kim Kyunghyun
• Kim Byeongju
• Nam Phil Ouk
• PARK Kwangchul
• Sohn Yeon-Sil
• Lee Jin-I
• JUNG Wonbong

Classifications

• G11C16/0466 Primary

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• H01L27/11568 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10B43/30 Primary

  characterised by the memory core region · CPC title