3D memory

Patent metadata

Field	Value
Publication number	US-9230986-B2
Application number	US-201514610755-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Jan 24, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

First claim

What is claimed is:

1. A method of forming a memory stack, the method comprising:
forming a plurality of control gates and control gate recesses between tier dielectric layers;
forming a first layer of dielectric material on the plurality of control gates in the control gate recesses;
forming barrier material in the control gate recesses and on the first layer of dielectric material;
removing portions of the barrier material to form barrier films adjacent to the control gates;
forming a second layer of dielectric material on the barrier films;
forming charge storage structure material on the second layer of dielectric material; and
removing portions of the charge storage structure material to form charge storage structures, each of the charge storage structures having a dimension that is substantially equal to a corresponding dimension of a respective one of the barrier films.

2. The method of claim 1 , further comprising:
before removing the portions of the barrier material, forming sacrificial material on the barrier material and removing portions of the sacrificial material; and
before forming the second layer of dielectric material, removing the remaining sacrificial material.

3. The method of claim 1 , wherein removing portions of the barrier material to form the barrier films includes removing the portions of the barrier material to form each of the barrier films to have a dimension that is substantially equal to a corresponding dimension of a respective one of the control gates.

4. The method of claim 1 , wherein forming the plurality of control gates comprises forming a plurality of polysilicon control gates.

5. The method of claim 1 , wherein forming barrier material comprises forming nitride.

6. The method of claim 1 , wherein forming charge storage material comprises forming polysilicon.

7. The method of claim 1 , wherein forming the memory stack includes forming a NAND memory stack.

8. A method of forming a memory stack, the method comprising:
forming a plurality of control gates and control gate recesses between tier dielectric layers;
forming a first layer of dielectric material on the plurality of control gates in the control gate recesses;
forming barrier material in the control gate recesses and on the first layer of dielectric material;
forming a second layer of dielectric material on the barrier material;
forming charge storage structure material on the second layer of dielectric material;
removing portions of the charge storage structure material to form charge storage structures, each of the charge storage structures having a dimension that is substantially equal to a corresponding dimension of a respective one of the barrier films;
removing portions of the barrier material to form barrier films adjacent to the control gates; and
forming a third layer of dielectric material on exposed surfaces of the plurality of control gate recesses.

9. The method of claim 8 , further comprising:
before removing the portions of the barrier material, forming sacrificial material on the barrier material and removing portions of the sacrificial material; and
before forming the second layer of dielectric material, removing the remaining sacrificial material.

10. The method of claim 8 , wherein removing portions of the barrier material to form the barrier films includes removing the portions of the barrier material to form each of the barrier films to have a dimension that is substantially equal to a corresponding dimension of a respective one of the control gates.

11. The method of claim 8 , wherein forming the plurality of control gates comprises forming a plurality of polysilicon control gates.

12. The method of claim 8 , wherein forming barrier material comprises forming nitride.

13. The method of claim 8 , wherein forming charge storage material comprises forming polysilicon.

14. The method of claim 8 , wherein forming the memory stack includes forming a NAND memory stack.

15. The method of claim 8 , wherein removing portions of the barrier material includes converting portions of the barrier to dielectric through an in situ steam generation process; and
the method further comprises etching dielectric material covering the barrier material.

16. A method of forming a memory stack, the method comprising:
forming a plurality of control gates in control gate recesses;
forming a first dielectric on each the plurality of control gates and in the control gate recesses;
forming a barrier film material in the control gate recesses and on the first dielectric;
forming a second dielectric on the barrier film material;
forming a charge storage structure on the second dielectric; and
removing a portion of the charge storage structure to form a charge storage structure having a dimension that is substantially equal to the corresponding dimension of the barrier film material in the control gate recess.

17. The method of claim 16 , further comprising removing portions of the barrier material to form barrier films adjacent to the control gates.

18. The method of claim 17 , wherein forming the barrier film material includes forming the barrier film material such that the barrier film has a face and forming the charge storage structure includes forming the charge storage structure to have a face opposing the face of the barrier film and substantially parallel to the face of the barrier film, wherein each part of the face of the barrier film is separated from the face of the charge storage structure by a substantially equal distance.

19. The memory of claim 17 , wherein forming the charge storage structure includes forming the charge storage structure to have a substantially planar side facing the barrier film, forming the control gate includes forming the control gate to have a substantially planar side facing the barrier film, and the forming the barrier film includes forming the barrier film to have a first substantially planar side facing and substantially parallel to the substantially planar side of the charge storage structure and a second substantially planar side facing and substantially parallel to the substantially planar side of the control gate.

20. The method of claim 16 , further comprising forming a third dielectric on exposed surfaces of the plurality of control gate recesses.

Assignees

• Micron Technology Inc

Inventors

• Hopkins John
• Fan Darwin Franseda
• Simsek-Ege Fatma Arzum
• Brighten James
• Mauri Aurelio Giancarlo
• Jayanti Srikant

Classifications

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D64/01 Primary

  Manufacture or treatment · CPC title